1. 1 8-bit X 8-bit SRAM and 3 X 8 Decoder Irina Vazir, Prabhjot Balaggan and Sumandeep Kaur Advisor: Dr. David Parent December 06, 2004

2. 2 Agenda Abstract Introduction Project Details Results Cost Analysis Conclusions

3. 3 Abstract We designed an 8-bit X 8-bit SRAM and a 3 X 8 decoder that operated at 200 MHz and uses 5.425 mW of Power and occupied an area of 462  m x 532  m.

4. 4 Introduction SRAM: Memory circuit that permits writing and reading, stored data can be retained indefinitely without any periodic refresh. 1-bit data storage cell: Full CMOS SRAM cell configuration. Equation used for wn and wp of the cell: (W/L) 3 / (W/L) 1 < 2(V DD – 1.5V T,n )1.5V T,n ( VDD – 2V T,n ) 2

5. 5 1-bit cell of the SRAM

6. 6 Project Details 8-bit X 8-bit SRAM that operates at 5ns. The project was divided into subsystems namely the SRAM cell, precharge circuit, sense amplifiers, write circuit, mux-based DFF’s and the decoder. Output of the decoder specifies address for the SRAM cells, where the data needs to be written or read from.

7. 7 SRAM Schematic #1

8. 8 SRAM Schematic #2

9. 9 SRAM Layout

10. 10 SRAM Test bench

11. 11 SRAM Verification

12. 12 SRAM simulation: Post Extracted

13. 13 SRAM Simulations

14. 14 Decoder Schematic

15. 15 Longest Path Calculations for the Decoder Note: All widths are in microns and capacitances in fF

16. 16 Decoder Layout

17. 17 Decoder Verification

18. 18 Decoder Simulation: Post Extracted

19. 19 Cost Analysis Task Number of days Verifying Logic: 4 days Verifying Timing: 7 days Layout: 8 days Post Extracted Timing: 1 day

20. 20 Lessons Learned Start early. Test at every phase. No IT support on weekends. Planning is very important.

21. 21 Summary We designed an 8-bit X 8-bit SRAM and a 3 X 8 decoder that operated at 200 MHz and uses 5.425 mW of Power and occupied an area of 462  m x 532  m. Future designs can definitely minimize area.

22. 22 Acknowledgements Thanks to our family members for putting up with us. Thanks to Cadence Design Systems for the VLSI lab. Thanks to Synopsys for Software donation. Thanks to Professor Parent for his guidance throughout the project.