Hsiang-Chieh Liao 01/15/04 FFAST: An FPGA Fault Simulation Tool for Stuck-at and Path-Delay Faults Laboratory for Reliable Computing (LaRC) Electrical.

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Presentation transcript:

Hsiang-Chieh Liao 01/15/04 FFAST: An FPGA Fault Simulation Tool for Stuck-at and Path-Delay Faults Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing Hua University Advisor: Jing-Jia Liou & Cheng-Wen Wu Student: Hsiang-Chieh Liao 2004

Hsiang-Chieh Liao 01/15/04 Outline Introduction FPGA Test FPGA Architecture Switch Matrix Models Input Files Test Configuration Fault Coverages –Stuck-at Fault –Delay Fault Simulation Flow –SAF –PDF Defect Injection Experimental Result Conclusion

Hsiang-Chieh Liao 01/15/04 Introduction FPGA is popular for design verification and prototyping We test unprogrammed FPGA Architecture and size complexity is increasing We present a fault simulator for FPGA test development and test evaluation

Hsiang-Chieh Liao 01/15/04 FPGA Test Programmed FPGAUnprogrammed FPGA CLBInterconnect (Need Test Pattern)(Need Fault Model & TCs)

Hsiang-Chieh Liao 01/15/04 FPGA Architecture A generic FPGA architecture CLB (1,2) CLB (2,2) IO (1,0) CLB (2,1) CLB (1,1) IO (2,0) IO (3,1) IO (3,2) IO (2,3) IO (1,3) IO (0,2) IO (0,1) Switch Matrix Switch Matrix Switch Matrix Switch Matrix Switch Matrix Switch Matrix Switch Matrix Switch Matrix Switch Matrix

Hsiang-Chieh Liao 01/15/04 Different Switch Boxes (a) Subset XC4000-series (b) Universal C. Wong (96’) (c) Wilton S. Wilton (97’)(d) Twist M. Sadowska (DAC03’)

Hsiang-Chieh Liao 01/15/04 My Switch Matrix Module Switch Matrix Compound CIP

Hsiang-Chieh Liao 01/15/04 Input Files Architecture file –FPGA array size, ex: 14x14 –Channel width –The number and the location of CLB pins –Routing constraints of CLB pins –The resource of Switch box Configuration file Defect file Spec file

Hsiang-Chieh Liao 01/15/04 Test Configuration ####FPGA Configuration Path OPIN (0,2) Pad:0 CHANX (0,1) Track:1 SWITCH (0,1) (0,1) HORIZONTAL SWITCH (0,1) (1,1) HORIZONTAL SWITCH (0,1) (2,1) HORIZONTAL CHANX (1,1) Track:1 IPIN (1,2) Pin:0 CLB (1,2) IO (1,0) CLB (1,1) IO (1,3) IO (0,1) Switch Matrix Switch Matrix Switch Matrix Switch Matrix Switch Matrix Switch Matrix G0 (0,2)

Hsiang-Chieh Liao 01/15/04 Fault Coverages The stuck-at fault ： Interconnect The delay fault ： Path delay fault, for BIST A. Lai (ITC02’)

Hsiang-Chieh Liao 01/15/04 FPGA Fault Simulaton Flow - SAF Start Read Inputs Arch. File Config. File Test pattern Construct FPGA P&R Another config ? Yes Stuck-at Fault Coverage Calculation DONE No Flag Covered Segment Feature Coverage

Hsiang-Chieh Liao 01/15/04 FPGA Fault Simulaton Flow - PDF Start Read Inputs Arch. File Config. File Defect File Spec. File sampleCNT Test pattern Construct FPGA P&R Inject Defect Another config ? Yes Delay Fault Coverage Calculation DONE Another Sample ? Yes No Any defect detected ? Yes No Delay Fault Coverage

Hsiang-Chieh Liao 01/15/04 Delay Fault Coverage Calculation Initialize K=1 K == N? Defect K Flagged ? Yes No Yes No K++ Search for a faulty path for each defect segments DONE N : defect count K : defect index Start A faulty path exist ? Faulty FPGAs ++ Yes No Detected FPGAs ++

Hsiang-Chieh Liao 01/15/04 Defect Injection Defect count –Mixed Poisson (C.H. Stapper 80’) –Discrete Exponential (H. Masuda 99’) Defect Location –Random, Poisson Defect Size –Poisson (C.H. Stapper 83’)

Hsiang-Chieh Liao 01/15/04 Different Defect Sizes Sample Count: 1K Each Segment Spec: 3.5 ns Defect Count (mean): 1.3 Slack over Spec: 10% (.35ns) FPGA Size: 14x14 Defect Size(ns) C-Delay Fault Coverage % % % % % % % % % Index ♪ C-Delay Fault Coverage : Conditional Delay Fault Coverage

Hsiang-Chieh Liao 01/15/04 Different FPGA Sizes FPGA Size 2x2 5x5 10x10 14x14 20x20 25x25 30x30 35x35 40x40 Delay Fault Coverage 89.95% 89.07% 89.09% 90.40% 87.11% 89.35% 89.88% 87.40% 87.44% Feature Coverage 45.56% 70.88% 83.64% 87.89% 91.29% 92.94% 94.06% 94.88% 95.50% Sample Count: 1K Each Segment Spec: 3.5 ns Defect Count (mean): 1.3 Slack over Spec: 10% (.35ns) Defect Size (mean): 1.75ns Eff-Feature Coverage 100% C-Delay Fault Coverage 91.49% 100% 99.44% 99.71% 98.91% 100% ♪ C-Delay Fault Coverage : Conditional Delay Fault Coverage

Hsiang-Chieh Liao 01/15/04 The Improvement of TCs CLB (1,2) CLB (1,1) Switch Matrix Switch Matrix Switch Matrix Switch Matrix Faulty Segment TCs Faulty Path Reported by FFAST, path slack(0.6) defect size(0.4) path slack(0.6) defect size(0.3) Faulty Segment IO (1,0) pad1 IO (1,0) pad0 IO (0,1) pad0 IO (0,1) pad1 IO (0,2) pad0 IO (0,2) pad1

Hsiang-Chieh Liao 01/15/04 Conclusion We have presented an FPGA fault simulator, called FFAST It eases the task of evaulating the testing methods With FFAST, we can improve the TCs to increase the FC much easier than ever We would like to support more FPGA architectures and more fault models in the future