1. A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, R.O.C.

2. Outline  Introduction  Constrained via minimization problem  Layer Assignment Algorithm  Special consideration  Experimental Flow and Results  Conclusions and Future Work

3. Introduction  Side effect of vias  Chip area, Performance, Yield, Reliability  Via minimization problem  Two layer CVM, Multi-layer CVM  Problem transformation  Practical consideration

4. Basic Terminology  Net  Via  Stacked via  Mutually exclusive wire segments  Connected wire segments M1 M3 Net 2Net 1 2 metal3 metal1 metal2 M2 1

5. Constrained Via Minimization (CVM)  CVM-K problem  n wire segments  k different layers  feasible assignment ( )  all design rules must be satisfied

6. Graph representation--G( )  Exclusive edge  Connected edge  Partitioning  Cut  Via Count 3 1 48 2 5 9 7 6 10 3 1 4 8 2 5 9 7 6 exclusiveconnectedNode partitioning 1 34 6 7 8 10 9 M1 M2 M3 M2M1 5 2

7. Problem Formulation  Feasible partitioning  Problem Transformation  Quality of partitioning  Feasible move  K-way graph-partitioning problem M1 M2 M3 2 M1 M2 M3 2 M1 M2 M3 2 1 34 a b a: valid edge b: invalid edge 1 1 feasible moveinfeasible move

8. Feasible Partitioning with Illegal Via 1 3 M1 M2 M3 Illegal via for metal 1 and metal 3 1 23 metal 1 metal 2 metal 3 exclusive connected Net 2 Net 1 2

9. Layer Assignment Algorithm  Simulated Annealing-based Optimization  Modification  Random selection  Sequential evaluation

10. Simultaneous Movement a1 a2 a1

11. Via Counting

12. Via Counting Example metal 3 1 2 3 metal1metal2 1 2 3 1 2 3 1 2 3 metal 1 via_no + 1 no change Connected edge An example of via counting

13. An Observation 1 2 3 4 5 6 7 Metal 1 Metal 2 Metal 3 Metal 1 Metal 2 Metal 3 4 1 2 3 5 6 7

14. Via Updating  Partial modification  An example 13 2 A B 13 2 A B 13 2 A B 1 Move node 1 to partition B Check node 2, mark 3 via_no + 1 Check node 3 via_no not changed

15. Special Consideration  Overlap consideration  I/O pin limitation  Over-the-cell constraint a2 a1 Net 1 Net 2 a1 a2

16. Experimental Flow Input Technology Mapping (SIS) Cell Library Verilog-In automatic P&R Edif-Out Edif Parser Result Our algorithm with interlock solution Our algorithm w/o interlock solution

20. Experimental Results

21. Conclusions  Formulating CVM-K problem as a constrained k-way graph partitioning problem  Modified simulated annealing based heuristic  High reduction ratio  Apply to large circuits  More effective than standard simulated annealing method

22. Future Work  Crosstalk reduction  Delay minimization  Antenna Effect Consideration