Presentation on theme: "A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing."— Presentation transcript:
A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan, R.O.C.
Outline Introduction Constrained via minimization problem Layer Assignment Algorithm Special consideration Experimental Flow and Results Conclusions and Future Work
Introduction Side effect of vias Chip area, Performance, Yield, Reliability Via minimization problem Two layer CVM, Multi-layer CVM Problem transformation Practical consideration
Basic Terminology Net Via Stacked via Mutually exclusive wire segments Connected wire segments M1 M3 Net 2Net 1 2 metal3 metal1 metal2 M2 1
Constrained Via Minimization (CVM) CVM-K problem n wire segments k different layers feasible assignment ( ) all design rules must be satisfied
Conclusions Formulating CVM-K problem as a constrained k-way graph partitioning problem Modified simulated annealing based heuristic High reduction ratio Apply to large circuits More effective than standard simulated annealing method