1. 1 A Min-Cost Flow Based Detailed Router for FPGAs Seokjin Lee *, Yongseok Cheon *, D. F. Wong + * The University of Texas at Austin + University of Illinois at Urbana-Champaign

2. 2 Outline Overview Introduction FPGA Architecture, Routing resources Problem Definitions Algorithm Description Min-cost flow based router Lagrangian relaxation Experimental Results Conclusion

3. 3 Overview FlowRoute - A congestion-driven detailed router Finds a feasible routing with minimum total delay for a given placed netlist. Routes all the nets connected to a LUT simultaneously by a min-cost flow algorithm Iterative refinement with Lagrangian relaxation

4. 4 FPGA Architecture Logic modules Implements logic functions LUTs, flip-flops Routing resources Wire segments Programmable switches I/O modules

5. 5 FPGA Routing Resources Prefabricated routing resources Congestion constraints Limited Routability High RC delays and large area of switches

6. 6 FPGA Routing Example

7. 7 Graph Representation Routing resource graph G (V, E) V : I/O pins of logic modules, wire segments E : feasible connections between the nodes Routing problem: Finding vertex disjoint trees T={T 1,…,T n }

8. 8 Problem Definitions The Routing for One LUT (ROL) Problem Find routes for all the net segments connected to a LUT Using equivalence of input pins of a LUT FPGA detailed routing problem Find routes for all the nets. Soving ROL problem for all LUTs in an FPGA

9. 9 Flow Network for ROL Construct G f (V f, E f ) from G(V, E) V f = V U {s, s 1, s 2, …, s n, t}, s i : subsource E f = E U E s U E s’ U E t E s = {(s, s i )| i = 1, …, n}, E s’ = {(s i, v)|i = 1, …, n, v in T i } E t = {(p i, t)| p i in S p } Edge capacity r f (e) = 1 for all e in E f Node capacity r f (v) = 1, for all v in V f – {s, t} Cost: c f (e) = c(e) for e in E, c f (v) = c(v) for v in V

10. 10 Flow Network (example)

11. 11 ROL_NF (example)

12. 12 ROL_NF (example)

13. 13 ROL_NF for ROL A min-cost max-flow f* in G f corresponds to a solution to ROL with minimum total delay cost. If |f*|=n, all the net segments connected to a LUT ROL_NF exactly solves ROL problem in polynomial time

14. 14 ROL_NF Algorithm ROL_NF 1. Construct G f (V f, E f ) 2. Assign costs and capacities 3. Run min-cost max-flow algorithm on G f (V f, E f ) 4. Derive routes for the nets from the computed flow

15. 15 Lagrangian Relaxation General technique for solving optimization problems with difficult constraints Original optimization problem is divided into subproblems Each subproblem is solved by repetitive application of ROL_NF Lagrangian multipliers guide the router

16. 16 Lagrangian Relaxation Original problemLagrangian subproblem

17. 17 LR for FPGA detailed routing Original problemLagrangian subproblem max{min L (x)}

18. 18 Solving Lagrangian Subproblem By rearranging terms, L (x) =  k  i (c i + i )x ik –  i i LS ’ = min{  k  i (c i + i )x ik } ROL_NF solves LS’ Set (c i + i ) as a cost of i c i = d i (delay term) * q i (congestion term)

19. 19 Updating Lagrangian Multipliers Subgradient Method : stepsize

20. 20 FlowRoute 1. Initialize 2. For each l k in L do 3. Rip up nets connected to l k 4. Call ROL_NF 5. Update costs and reset capacities 6. Update 7. Repeat Step 2 – 6 until no shared resource exists

21. 21 Experimental Results FPGA model used Symmetrical-array-based FPGA Each logic block contains four 4-input LUTs and flip- flops Switch connections: F s = 3, F c = W F s : number of connections per wire entering the switch box F c : number of tracks to which each logic block pin can connect W : number of tracks in a channel

22. 22 Experimental Results Tested on MCNC benchmark circuits Results compared with VPR router Used smaller number of routing tracks Improvement on critical path delay up to 28.9 % (average 14.1%) Total wire length reduced (ave. 8.3%)

23. 23 Experimental Results Channel width and delay comparison CircuitsLUTs / FFs Number of tracksCritical Path Delay VPRFRVPRFR 9symml10410926.725.1 (6.0%) term1128131225.323.3 (7.9%) apex725213 26.121.3 (18.4%) example2404171629.623.2 (21.6%) alu222417 54.749.2 (10.1%) Too-lrg20819 31.230.2 (3.2%) vda45623 46.538.9 (16.3%) alu4156033 143.4122.5 (14.6%) s298196027 274.0194.7 (28.9%)

24. 24 Conclusion A new congestion-driven routing algorithm for FPGAs Find a feasible routing with minimum total delay – expects reduced critical path delay Can be used in multiple stage routing scheme

25. 25 Thank You!