2. A New Hybrid FPGA with Nanoscale Clusters and CMOS Routing Reza M. P
A New Hybrid FPGA with Nanoscale Clusters and CMOS Routing Reza M.P. Rad and Mohammad Tehranipoor University of Connecticut Design Automation Conference, 2006

3. Outline Introduction/Background Motivation/Contributions
CMOS Logic Cluster Architecture
Nanowire-based Cluster
CMOS Support
Experiment Setups
Results (Area/Performance)
Conclusion

4. Introduction Challenges in further scaling CMOS
Various nanoscale and molecular-electronics based devices under research
Various assembly techniques experimented
Self-assembly and nano-imprint techniques provide regular array structures (crossbars)
Molecules with switching properties
Reconfigurable switches
CMOS support can provide inputs/outputs/configuration circuitry for nanoscale devices.

5. Background
CMOS-Nano interface based on modulated doping of nanowires [DeHon, JETC’05]
DMUX based on random deposition of gold particles on nanowire array [Kuekes, 2000]
Single bit decoder-like interface [DeHon, JETC 2005]
PLA-based FPGA architecture [DeHon, JETC’05]
Island style architecture for nanoscale devices [Goldstein, 2001]
Cell-based architecture (CMOL) [Likharev, 2005]

6. Background
Using nanowires as FPGAs’ interconnects were analyzed in [Gayasen, DAC 2005]
Hybrid-FPGAs with CMOS clusters and nanowire routing were considered
It was reported that using nanowire interconnects in FPGAs can reduce area up to 70%
Effects of nanowire-based implementation of logic clusters on area and delay were not reported

7. Motivation Design a new hybrid FPGA
Emerging nanotechnologies require a CMOS-scale support that provides I/O and configuration circuitry
Analyze efficiency of hybrid CMOS-Nano devices
A hybrid FPGA with nanoscale clusters
Perform experimental evaluations to provide insights to benefits and challenges of such hybrid technologies

8. Contribution
New hybrid FPGA with nanoscale cluster and CMOS interconnects
A logic cluster architecture based on crossbars of nanowires is proposed for FPGAs
The proposed cluster has the same functionality as traditional CMOS clusters
FPGA tools are modified to model area and performance based on the proposed cluster
Results show significant area reduction for hybrid FPGA while the performance is slightly degraded.

9. Logic Cluster Architecture
LUTs and MUXes are the most area consuming parts of any cluster
MUXes can take up to 70% of the area
Reducing the size of LUTs and MUXes, will considerably reduce the overall area of the FPGAs
K input
LUT
out
DFF
Basic Logic Element (BLE)
BLE1 N
Out
BLE N
I In
Logic Cluster in FPGAs

10. LUTs Implemented on Crossbars
LUTs and MUXes can be implemented on nanowire crossbars
Diodes of each column are configured to make one of the minterms
Diodes on output line are configured to provide sum of minterms
f = ∑Minterms(1,2,4,2 −1) k

11. Nanowire-based (Nanoscale) Cluster
A crossbar can be configured as several LUTs and MUXes
It has the same functionality as CMOS clusters used in FPGAs
(I) : cluster I/O
(II) : To DFFs
(III) : Config. Addr.
I/O and Config MUXes proposed
in [Kuekes,2000] or [Rad, 2006]

12. CMOS Support CMOS support circuitry for the proposed cluster
CMOS Substrate
CMOS support circuitry for the proposed cluster
Provides inversion, latching and configuration addresses
It can be implemented on the substrate under the nanoscale crossbar to minimize the area

13. SIS (FlowMap and FlowPack): Maps Netlist to K-input LUTs
Experiment Setups
MCNC Benchmarks
(Netlist)
Area and delay for routing components and clusters should be estimated and applied to VPR
Realistic values to resistors and capacitors of switches and line segments
VPR calculates area based on number of min-size transistors
SIS (FlowMap and FlowPack):
Maps Netlist to K-input LUTs
T-Vpack: Packs K-LUTs
Into clusters of size N
VPR: Performance
Driven placement
and routing
Architecture Model
For:
(I) Full-CMOS
FPGA (22 nm)
(II) Hybrid FPGA
Area and Delay
Results

14. Results: Area Average area for implementing 77 MCNC benchmarks
K : LUT size
N : Cluster size
Area of Hybrid FPGA is significantly lower than CMOS FPGA 2
CMOS FPGA
(22 nm)
N=8
Average Area um
28500
N=2
K (# of LUT Inputs) 2
Hybrid FPGA
Average Area um
12500
K (# of LUT Inputs)

15. Results: Area (Hybrid FPGA)
The increase in area of LUT and MUXes will be small when K increases (nanowire crossbars)
Inter-cluster routing area decreases when K increases
Area of hybrid FPGA will not increase with increase in K
Up to 75% area reduction compared to CMOS FPGA
Area Reduction % 4 5 6 7 2
18.3
23.6
32.5
46.8
29.5
43.8
53.9
64.6
44.3
50.6
59.3
68.5 8
45.9
55.1
69.1
75.7 K N

16. Results: Delay
Average critical path delays for different values of K and N for 77 MCNC benchmarks
K : LUT size
N : Cluster size
Delay parameters for 22 nm CMOS were estimated based on [Sylvester & Kuetzer 1998]
Nanowire RC parameters calculated based on [DeHon, JETC’05]
CMOS FPGA
(22 nm)
Critical Path Delay (S)
K (# of LUT Inputs)
Hybrid FPGA
N=8
Critical Path Delay (S)
N=2
K (# of LUT Inputs)

17. Results: Delay
In CMOS FPGAs, delay of the cluster will increase when K increases
Increasing K will reduces the number of inter-cluster routing wires on critical path
The results show that increasing K and N will slightly reduce the critical path delay for CMOS FPGAs
CMOS FPGA
(22 nm)

18. Results: Delay
In Hybrid FPGA, delay of the cluster depends on resistance and capacitance values of the nanowires
As K and N increase, the length of nanowires used in the cluster will increase
Hence delay of the cluster considerably increases
Therefore, for hybrid FPGA, increasing K and N will increase critical path delay
Hybrid FPGA
N=8
N=2

19. Conclusions A new hybrid FPGA was proposed
The proposed cluster was based on nanowire crossbars
The FPGA tools have been modified to implement MCNC benchmarks on the proposed hybrid FPGA
Hybrid FPGAs showed area reductions of up to 75% compared to 22 nm CMOS FPGAs
Performances of CMOS and Hybrid FPGAs are almost equal for average size clusters

20. Future works
Application of experimental data of nanowire based devices to the models to obtain more accurate comparison measures
Perform power analysis to evaluate power requirements of nanowire based circuits
Investigation of more efficient implementations of logic clusters based on nanowires
Reliability and fault tolerance of nanoscale components must be investigated.