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B UILT -I N S ELF -T EST OF G LOBAL R OUTING R ESOURCES IN V IRTEX -4 FPGA S Jia Yao, Bobby Dixon, Charles Stroud and Victor Nelson Dept. of Electrical.

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Presentation on theme: "B UILT -I N S ELF -T EST OF G LOBAL R OUTING R ESOURCES IN V IRTEX -4 FPGA S Jia Yao, Bobby Dixon, Charles Stroud and Victor Nelson Dept. of Electrical."— Presentation transcript:

1 B UILT -I N S ELF -T EST OF G LOBAL R OUTING R ESOURCES IN V IRTEX -4 FPGA S Jia Yao, Bobby Dixon, Charles Stroud and Victor Nelson Dept. of Electrical & Computer Engineering Auburn University

2 North Atlantic Test Workshop2 J. Yao 5/15/08 2 Outline of Presentation  Motivation and background  Virtex-4 global routing resource  Routing BIST Implementation for Virtex-4 FPGAs for Virtex-4 FPGAs  Implementation results  Application to Virtex-5  Summary

3 North Atlantic Test Workshop3 Fault Simulation Results Stuck-at Fault  Stuck-at value  Feedback wires can be considered can be considered under test under test Bridging Fault  Best approaches  8-bit maximum length sequence CAR sequence CAR  cross-coupled parity J. Yao 5/15/08

4 North Atlantic Test Workshop4 Cross-Coupled Parity Approach F LUT G LUT Podd Cd1 Cd0 F LUT G LUT Peven Cu1 Cu0 Slice 0 Slice 2 Slice 1 Slice 3 TPG (Te) count-up even parity TPG (To) count-down odd parity ORA (Oe) even parity ORA (Oo) odd parity 2 1 1 2 ORA even parity ORA odd parity G LUT Podd Cu1 Cu0 Pass /Fail G LUT Peven Cd1 Cd0 Pass /Fail Test Pattern Sequence Cu 1 Cu 0 PoCd 1 Cd 0 Pe 001110 010101 0011 111000 J. Yao 5/15/08

5 North Atlantic Test Workshop5 Virtex-4 Global Routing Resources  CLB  Switch Box  Slices (LUTs & FFs)  PIPs  Double/Hex lines  N/S/E/W  10 wires  BEG, MID, END  Long Lines Switch Box N/S 2 BEG 0-9 N/S 2 MID 0-9 N/S 2 END 0-9 slices Long lines J. Yao 5/15/08

6 North Atlantic Test Workshop6 BIST for Double lines (North and South) Test Pattern Sequence Cu 1 Cu 0 PoCd 1 Cd 0 Pe 001110 010101 0011 111000  Pass by 1 CLB into MID pass by 2 CLBs into END  6 wires under test (2 configs)  12 lines under test in parallel  Alternate TPGs, ORAs position in adjacent CLBs. J. Yao 5/15/08

7 North Atlantic Test Workshop7 Loopbacks South END-to-BEG Connections Loopback Connections   At the edges of array   via wires in the opposite direction till the opposite edge   Example: north double lines loopback at the top edge J. Yao 5/15/08

8 North Atlantic Test Workshop8 BIST for Double lines (East and West)  Involve Non-CLB Columns  END and BEG terminals in east and west directions are connected J. Yao 5/15/08

9 North Atlantic Test Workshop9 Non-CLB Column Double Lines  BIST for Non-CLB Column Double Lines  TPGs and ORAs locate in adjacent CLB columns  Use east/west double lines to connect adjacent CLB columns J. Yao 5/15/08

10 North Atlantic Test Workshop10 BIST For Hex Lines   Hex lines architecture   pass by 3 CLBs into MID, by 6 CLBs into END   more limitation of connections from hex lines to LUTs   MID and END terminals share the same PIPs   BIST for hex lines   similar to double lines   more configurations needed J. Yao 5/15/08

11 North Atlantic Test Workshop11 Long Lines Architecture   pass by 24 CLBs   5 wire segments 4 wires under test   Bi-directional   two end points: source or input   other three stops: input only   Orthogonal direction is tested simultaneously i i+1 i+6 i+7 i+12 i+13 i+18 i+19 i+24 i+25 J. Yao 5/15/08

12 North Atlantic Test Workshop12 BIST for Long lines Oe Tcu Tcd Peven Cuo Cu1 Cu2 Peven CLB i CLB i+6 CLB i+12 CLB i+18 CLB i+24 G LUT Peven Cd0-3 Pass /Fail F LUT ORA even parity (Oe) TPG count-up even parity (Tcu) TPG count-down even parity (Tcd) Cu2 Cu1 Cu0PevenCd2 Cd1 Cd0Peven 0 0 001 1 11 0 0 111 1 00 0 1 011 0 10 0 1 101 0 01 10 1 10 1 0 100 1 01 1 1 000 0 11 1 1 110 0 00 CLB i+2 CLB i+1 CLB i CLB i+3 CLB i+4 CLB i+5 J. Yao 5/15/08

13 North Atlantic Test Workshop13 Global Routing BIST Configurations Routing Resource Direction Total Configs NSEW CLB double lines 2222 8 Non-CLB column double lines224 CLB hex lines442212 Non-CLB column hex lines224 CLB long lines**112 Non-CLB column long lines112 Total BIST Configurations3232 J. Yao 5/15/08

14 North Atlantic Test Workshop14 RAM DSPMIDDLE Actual Implementation Results I/O Cell J. Yao 5/15/08

15 North Atlantic Test Workshop15 Application to Virtex-5   Global Routing Resource changed   double lines, pent lines and long lines   N/S/E/W   BEG, MID, END   half as the same, half as “L-shaped” which go in orthogonal direction as well   3 wires for each pattern in each direction instead of 10   long lines pass by 18 CLBs, four wires   Our approach is adapted to Virtex-5   test for “L-shaped” double/pent lines J. Yao 5/15/08

16 North Atlantic Test Workshop16 Summary  Cross-coupled Parity is the best choice  better fault coverage  the most practical for actual implementation  best choice for Virtex-5  BIST of Virtex-4 routing resources  Program to generate BIST configurations automatically  modified for V-5 J. Yao 5/15/08

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