Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 6: Feb. 25 th Simulation Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost Design Manager: Steven Beigelmacher

Status Design Proposal (done) Architecture (done) High Level C Simulation Behavioral Verilog & Test Bench Floorplan & Structural Verilog Gate Level Design (done) Top Level Schematic Verification Component Layout (done) Analog simulation of SRAM and ROM Layout of all components Component Simulation (90%) Still to be done Top level layout Top level simulation

12bit Input Reg 8X10 SRAM Value Look-up 12bit Input Reg Engine Speed Manifold Pressure 12bit Input Reg Throttle Position Fixed Point Array Multiplier 2:1Mu x 12bit Output Register Control ROM 12bit Input Reg %Oxygen 7X4 SRAM Comparator Look-up 4:1Mux = R0 12bit Register Win Sin[0:1] 2:1Mu x Rcomp Sin[0:1] Index[0:4] Write R1 R2 RowComp[0]RowComp[1] Srow1 Srow2 RowComp[2] 3bit Reg Wcol Index[0:6] Write Rtable 2:1Mu x Scol ColTable[0:3] 2:1Mu x Scol Valid Wmult1 Wmult2 Smult 5bit State Reg Next[0:4] Wout PulseOut[0:11]

Happy Bill Gates Day!

Simulations Used 10f F on output except for the DFF which used 50f F Rise/Fall go from 10%-90% Two minimized inverters on every input.

8x10 SRAM

7x4 SRAM

ROM

DFF

Comparator

4:1 Mux

Top Level Layout (old)

Top Level Layout (new) 390X430 (µm) With Tetris Upgrades

Questions????