The Origami Chip-on-Sensor Concept for Low-Mass Readout of Double-Sided Silicon Detectors M.Friedl, C.Irmler, M.Pernicka HEPHY Vienna

2Markus Friedl (HEPHY Vienna)17 Sept 2008 Motivation: Belle Belle Silicon Vertex Detector (SVD2) –4 layers, total of 246 double-sided silicon detectors (DSSDs) –17°…150° polar angle coverage –Slow readout: ~800ns peaking time Low energy machine: Material budget is extremely important!

3Markus Friedl (HEPHY Vienna)17 Sept 2008 SuperKEK-B Upgrade Planned for –Ultimately 30-fold increase in luminosity and trigger rate SVD2 Limitations: –Occupancy (currently ~10% in innermost layer)  need faster shaping –Dead time (currently few percent)  need faster readout and pipeline APV25 readout chip would fit the needs Requirements similar to ILC SVD2 occupancy vs. layer

4Markus Friedl (HEPHY Vienna)17 Sept 2008 APV25 Developed for CMS by IC London and RAL 40 MHz clock 128 channels 192 cells deep analog pipeline 50 ns (adjustable) shaping time 0.25 µm CMOS process (>100 MRad tolerant) Low noise: 250 e + 36 e/pF Multi-peak mode (read out several samples along shaping curve)

5Markus Friedl (HEPHY Vienna)17 Sept 2008 Shaping Time and Occupancy BEAM PARTICLE } OFF-TIME BACKGROUND PARTICLE }

6Markus Friedl (HEPHY Vienna)17 Sept 2008 Shaping Time and Noise Unfortunately, short shaping time inherently implies larger noise Applies to both constant term and slope –VA1TA (Tp=800ns):ENC = 180 e e/pF –APV25 (Tp=50ns):ENC = 250 e + 36 e/pF Nothing can be done about constant term Capacitance must be minimized to reduce effect of steeper slope

7Markus Friedl (HEPHY Vienna)17 Sept 2008 SVD2 Ladders Up to 3 ganged (concatenated) sensors are read out from the side Minimization of material budget, as hybrids are outside of acceptance SNR >> 15 with VA1TA, but would be << 10 with APV25 Ganging of sensors does not work with APV25! up to 3 ganged sensors up to 3 ganged sensors

8Markus Friedl (HEPHY Vienna)17 Sept 2008 Ganged Sensors Read Out with APV25 Prototype module with 2 partially ganged DSSDs gangedsingle p-siden-sidep-siden-side Cluster SNR Single Strip SNR Beam test result shows that already ganging of 2 sensors is problematic

9Markus Friedl (HEPHY Vienna)17 Sept 2008 Solution: Chip-on-Sensor Thinned APV25 with flex circuit (Kapton) sits on sensor Providing shortest possible connections to the strips (drawing not to scale)

10Markus Friedl (HEPHY Vienna)17 Sept 2008 Flex_Module Demonstrator prototype with chip-on-sensor readout on the n-side and conventional readout on the p-side Cooling pipe made of carbon fiber (too massive) n-side: chip-on-sensorp-side: conventional readout

11Markus Friedl (HEPHY Vienna)17 Sept 2008 Measurement Results Beam test result shows that chip-on-sensor (n-side) delivers excellent SNR Flex_ModuleConventional (single sensor) p-siden-sidep-siden-side Cluster SNR Single Strip SNR

12Markus Friedl (HEPHY Vienna)17 Sept 2008 Cooling Options Each APV25 dissipates ~350 mW In total, SuperBelle SVD will burn >1 kW  cooling mandatory Several options tried in “thermal channel“ with dummy APVs: –Air –Water –Heat pipe –TPG Clearly liquid cooling is most powerful option Paraffine: reduces risk of leakage and corrosion (used for beam pipe cooling in Belle)

13Markus Friedl (HEPHY Vienna)17 Sept 2008 Origami Concept Extension of chip-on-sensor to double-sided readout Flex fan-out pieces wrapped to opposite side (hence “Origami“) All chips aligned on one side  single cooling pipe Side View (below)

14Markus Friedl (HEPHY Vienna)17 Sept D Rendering

15Markus Friedl (HEPHY Vienna)17 Sept 2008 Material Budget X 0 comparison between conventional and chip-on-sensor: +50% increase in material, but also huge improvement in SNR Trade-off between material budget and SNR According to simulation, additional material is prohibitive in 2 innermost layers, but no problem for layers 3-5

16Markus Friedl (HEPHY Vienna)17 Sept 2008 Possible SuperBelle Layout Using 6“ DSSDs (~12.5 cm long, up to ~4 cm wide) Every sensor is read out individually (no ganging) –Edge sensors (green) are conventionally read from side –Center sensors (red) use chip-on-sensor concept (layers 3-5) layers [cm]

17Markus Friedl (HEPHY Vienna)17 Sept 2008 Summary & Outlook Motivated by Belle upgrade (requirements similar to ILC) APV25 chip (developed for CMS) fits Fast shaping implies higher noise Need to minimize capacitive load  chip-on-sensor concept Successfully demonstrated on Flex_Module “Origami“ concept for low-mass double-sided readout with cooling Will construct such a module in near future

18Markus Friedl (HEPHY Vienna)17 Sept 2008 Try It Yourself

19Markus Friedl (HEPHY Vienna)17 Sept 2008 BACKUP SLIDES

20Markus Friedl (HEPHY Vienna)17 Sept 2008 Comparison VA1TA – APV25 VA1TA (Belle SVD2) Commercial product (IDEAS) Tp = 800ns (300 ns – 1000 ns) no pipeline <10 MHz readout 20 Mrad radiation tolerance noise: ENC = 180 e e/pF time over threshold: ~2000 ns single sample per trigger APV25 (SuperBelle) Developed for CMS by IC London and RAL Tp = 50 ns (30 ns – 200 ns) 192 cells analog pipeline 40 MHz readout >100 Mrad radiation tolerance noise: ENC = 250 e + 36 e/pF time over threshold: ~160 ns multiple samples per trigger possible (Multi-Peak-Mode)