1. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 1

2. 2 Some general remarks about occupancy reduction An advanced method using the APV25 front-end chip How it could be realised for the upgrade of SVD2 @ Belle Contents

3. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 3 What are the problems and effects with high OCCUPANCY ? BELLE definition: every strip above threshold plus 2 neighbours for every cluster, divided by the total number of strips Effect depends on the number of layers and the spatial resolution. Above a certain size, occupancy creates fake tracks. Track finding becomes more complicated and the results are of lower quality. The detection of track points is reduced. Therefore an increase of beam intensity ( with included background) can reduce the performance of a detector, thus the number of useful events and finally also the physic results.

4. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 4 Possibilities to reduce the effects of the occupancy: A. reduction of the sensitive area/channel of the detector. Finally you will end up with a Pixel detector with an area of e.g. 100*150 µm 2 like CMS. The occupancy at CMS will be around 0.1%. The sensitive time window for a trigger will be around 25-30 ns. CMS Pixel ASIC would not be optimal for continuous beam (because it is designed for bunched LHC beam clock synchronised ). T Threshold for internal trigger around 2500 electrons

5. B. with the reduction of the shaping time. The APV25 offers a range of 450 ns down to 35 ns (designed for 50ns). Threshold Even a short peaking time (~50ns) creates a wide sensitive time window (~160ns) above threshold.

6. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 6 Single or multi peak mode Pipeline 192 cells Multi event buffer for 30 event-triggers with single hit read out, multi hit mode 10 event-trigger. Calibration system, 8 time steps per clock, max charge 25 fC Readout speed: clock frequency or half clock frequency, for data multiplexing at CMS Output levels adjustable 0.25µm CMOS: radiation hard (>100MRad) Works up to 80 MHz (samples tested but not guaranteed) 1.25, 2.5 Volt supply Clock, trigger/cal/reset and output are differential signals Some more details about the APV25

7. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 7 APV25 Analogue data processing

8. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 8 C. A further improvement: Reduction of the sensitive time area with analogue data processing. You need 3 analogue values of the shaped signal. These signals are combined with different weights, resulting in a pulse with reduced width. The APV25 has this possibility called “deconvolution mode”. + The time sensitive window is reduced by a factor of ~ 4 - Can only be used for beam intersection every 25 ns 40 MHz  not for continuous beam! - S/N reduced measured

9. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 9 The APV25 has the possibility to store 3 consecutive samples (spaced by the system clock) of a signal with one trigger (multi-peak mode). With a second trigger just 3 clocks later, you can get the next 3 time samples of the shaped input signal. We can use this mode to determine the peak time of the shaped detector SIGNAL relative to the CLOCK. We can also measure the time between the TRIGGER and the (APV25) CLOCK. (Continuous beam: trigger can come at any time related to the clock.) Comparing those 2 timing values we can select if the hit belongs to the event or reject as background if it is out of the selected time window (~20 ns). D. External Pulse Shape Processing

10. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 10 + Time of the trigger to the clock t=A = t=B t=A t=A t=B t=A Time of the hits Eliminating background using time information

11. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 11 12 time slices of a shaped input signal created by 4 triggers spaced by 3 clocks (Beam test CERN August 2004) We can use 3 or more pulse height values for time calculation.

12. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 12. S1 S2 S3 Trigger D Clock 40 MHz clock Sampling clock Q S1 S2 S3 Unsynchronised trigger Clock synchronised trigger Clock The time between these 2 signals must be measured TDC Calculate peak time to clock

13. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 13 M. C. signal with noise Accepted as signal above threshold Selected with S1,S3<=S2Selected S1<S3<=S2 and S3<S1<=S2 ~230 ns <50ns ~25ns Threshold As signal detected time width ~230 ns

14. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 14 Unsync'd Trigger Sync‘dc‘d Clock phases 1 1 1 2 2 2 3 3b 3a 4 4 4 1' First sample Peak Peak time is measured from first sample Trigger delay is measured between unsync'd and sync'd triggers Trigger delay Peak time Trigger delay +Peak time = constant = distance of Unsync'd Trigger to Peak despite of clock phase wrapping Shaping curve

15. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 15 Comparison of APV25 output waveforms (Tp=50ns): Simulation (ideal=Dirac current pulse), Simulation (real=realistic detector current pulse), Measurement (internal calibration), Measurement (extracted from particle signals) …and with the knowledge of the shaping curve, it is possible to obtain the peak time with ns precision. Knowledge of shaping curve important for the precision of the time measurement. Expect that every input channel of the APV25 has the same shaping curve.

16. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 16 2000ns above threshold = accepted as signal 160 ns above threshold Reduction factor ~12.5 Reduction factor comparing VA1TA (current Belle SVD readout ASIC) and APV25: VA1TA shaping time 800ns 2000ns above threshold APV shaping time 50ns 160 ns Using time information of signal and trigger to clock 160 ns ~20 ns Reduction factor ~8 Total reduction ~100 Cost: something needs an APV25 readout system No extra Cost: requires some extra processing power

17. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 17 Correlations with double-sided readout For matching hits in p and n sides, the following data are correlated and can be used to create a fast trigger: 1)time of the hit 2)pulse height 3)cluster size (if particle has same angle against both strips, like the UV-striplet detector proposed for Super-Belle) These correlations can be used to remove ambiguities, eliminate ‘ghost hits’ and thus reduce background A requirement on the cluster size can be used to reject hits from tracks with don’t originate from vertex

18. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 18 same amplitude same time same cluster width t=C t=B t=A t=A and t=B t=B and t=C t=A With time information it is possible to determine the hit point(s) and judge if a cluster contains one or more hits in most cases. Using 6 time slices t=A t=a

19. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 19 To get a impression of the possible time resolution of the processed 3 time slices of a hit, we use the p and n side data of a UV-striplet detector with APV25 readout obtained in a beam test. The trigger time has no influence on the result.

20. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 20

21. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 21 Correlation plots u-v pulse height time information cluster width (vertical incidence)

22. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 22 (const-TDC) vs. fitted peak time Residuals RMS=2.16ns (including scintillator trigger jitter)

23. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 23 Beam only run056 Source only run048 Beam + Source run050 ~same statistics for beam and source Top row: peak time distribution Bottom row: Signal distribution Time in ns

24. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 24 Beam only run056 Beam + Source + Peak time cut run050 Removal of source (background) by peak time cut Sensitive time window reduced to 20ns

25. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 25 Fitted peak time residuals vs. SNR P-sideN-side Time resolution (RMS residuals as as function of S/N) As expected this method suffers with low S/N

26. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 26 ideal trigger with little jitter (~3ns) trigger with jitter We need more time slices when the trigger has more time jitter and the method is compromised. A trigger with good time resolution in combination with an APV25 multi-hit readout system dramatically reduces the computing time and opens new possibilities at extremely high luminosity With a reduced trigger time information we can still find hits which fit to a track but the selection quality to an event is reduced. Jitter ~20ns + 3 ns of trigger

27. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 27 3 requirements for this system: A. Trigger for the APV25 readout system with good time resolution. RMS as small as possible, ideally <3 ns B. Delay for trigger <160 clock cycles C. Good S/N

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31. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 31 A lot more data has to be handled. Therefore we propose a signal processor on the ADC module. 3-6 times more data in multi-hit compared to single mode. Therefore every input should have its own data pipeline processor for hit finding. The processor could handle a trigger rate up to 30- 40 kHz and an occupancy of 3-4%. Limited mainly by the output connection to the DAQ. It is open how far we want to go in hardware data processing on the module. Anyhow it is foreseen to switch between three different modes: - data above a threshold with coordinates - transparent and processed data together in a block - hit data with peak time information We can realize that using a modified CMS Pixel read out module

32. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 32 D.P.M Reordered Memory Reorder : result 1 to 128 Hit finding Time calculation Hit finding on strips + neighbours with 2 steps of common mode correction De m ux muxmux Looks for the time between clock and signal + delay of 128 clocks + delay of 4*128 clocks + delay of ….. 0,32,64,96 | 8,40,72,104 | 16,48,80,112 | 24,56,88,120 || 1,33,65,97 | 9,... O,1,2,3,4,…128 Exists and working exists and working hardware exists Still some work to optimise… 9 channels are processed at the moment in one FPGA, this number could be reduced, because the FPGA also has its limits. Channel x

33. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 33 The prototype FADC + Processor Electrical input board instead of optical receiver Clock- control signal Mezzanine card for LAN output and further data processing

34. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 34 Summary: We are confident that we can eliminate occupancy problems of the BELLE Vertex detector for several years

35. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 35

36. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 36 Backup slides

37. Vertex 2005, Nikko Manfred Pernicka, HEPHY Vienna 37 pileups Time (x20ns clock frequency) PSI beam test (August 2005): high intensity and inclined detector Operation with beam synchronous 50MHz clock Amplitude (e) Each colour = signal of a cluster