1. WG3 – STRIP R&D ITS - COMSATS 02.5.2011 P. Riedler, G. Contin, A. Rivetti – WG3 conveners

2. Outline  Aims of the strip upgrade  The present ALICE strip detector (SSD)  Proposal for a new sensor design  Ideas for the detector layout  Micro-cables for interconnections  ASIC specifications and development  Plans for assembly tests 2 Strip R&D

3. Aims of the strip upgrade 3  Cover a large area on the outer (2-4) ITSupgrade layers B. 2 layers (present SDD)~ 1.3 m 2 C. 4 layers (present SDD &SSD) ~ (1.3 + 5) m 2  Manage higher multiplicity w/ low occupancy even at small radius (15 cm) to replace SDD  Provide tracking information w/ good resolution Spatial resolution: at least 20  m (r  ), 800  m (z) as the present SSD Connect tracks to TPC  Provide dE/dx for an improved PID over a dynamic range 0-15 Mips (for light nuclei & low mom. part.) with 0.1 Mip resolution (to separate different particle types) Strip R&D

4. The present ALICE strip detector: SSD 4 Strip R&D

5. R&D for the ALICE strip upgrade 5  Start from the present strip technology which is optimized for the present experimental conditions  Improve the strip system to meet the new ITS upgrade requirements (occupancy, data-format, acquisition rate, time resolution, extended PID,...)  Benefit from the past experience to get better reliability and uniformity of components Strip R&D

6.  The new strip sensor layout is being designed (Trieste group)  decrease the strip length from ~40mm to 20mm  cell size ~ -50%  C strip ~ -50%  2 x # of channels  same cluster size  2 rows of strips per sensor side Strip sensor layout draft 6 Strip R&D

7. Strip  cables design proposals  Double no. of channels requires a new Al-polymide  cable design draft 7 Strip R&D

8. Interconnection layouts & options 8  TAB bonding technique (allows chip tests, less material, safe folding)  Wire bonding (easier alignment) draft Strip R&D

9. Strip interconnections:  -cables  Discussion about specs with the Kharkov Group  Present SSD min trace pitch: 80  m  Past experience with prototypes: 46  m min. trace pitch 56  m min. trace pitch  Possible development of  cables with pitch ~ 50 um bonding and alignment becomes challenging needs to develop: new assembling technology sensor/ASIC/cables mock-ups for tests new hybrid (cable+chip) design 9 Strip R&D

10. Plans for assembly tests 10  Next steps:  Design the mask for a dummy strip sensor  Define the specifications for micro-cable prototypes  Evaluate different bonding techniques  Plan the production of the first dummy components  by the summer of 2011  Organize an assembly and bonding test with dummy components  by the end of 2011 Strip R&D

11. ASIC development 11 ASIC specsHAL25 (Present SSD)Upgrade target CMOS technology0.25 µm0.13 µm (?) Input pitch80 µm~44 µm On 2 staggered rows (?) ASIC size3.65 x 11.90 mm 2 5-6 x 6 mm 2 (?) Dynamic range1MeV ~290000 e- ≿ 1.3MeV (15 Mip) ~360000 e- Charge resolution~1 keV ~290 e- ~1 keV (0.1 Mip) ~290 e- Noise (ENC for 5 pF load cap.)< 300 e-  Investigating for available solutions for strip ASIC front-end chip: contacts with UK and CERN Groups  Specification definition in progress: Strip R&D

12. ASIC specifications 12 ASIC specsHAL25 (Present SSD)Upgrade target Peaking time1.4 – 2.2 µs≤1 µs Readout & FormatSerial, analogueDigital (?) ADCOff-detectorOn chip (?) Common Mode correctionOff-detectorOn chip (?) Power dissipation [µW] : 265 - 360 Readout: 680 - 759 Acquisition: 290 – 355 Better than present # channels per chip128 Total # of channels2.6 M~1 – 5 M (?) Expected Dose/Hadron Fluence (10 years) //30 kRad (TID) 6*10 11 cm -2 (hadron fluence in 1MeV n) Strip R&D

13. Summary 13  The aims of the strip upgrade are well defined  Clear ideas for the detector layout  Strip sensor design in progress  Different proposals for interconnections  Front-end ASIC: specs definition ongoing looking for partners to develop the chip  Test w/ dummy components to evaluate the assembly feasibility is planned Strip R&D