1. Status of SVD Readout Electronics Markus Friedl (HEPHY Vienna) on behalf of the Belle II SVD Collaboration BPAC October 2012

2. Introduction  I will focus on the readout chain between front-end and FTB  COPPER already belongs to the unified DAQ 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics2 Front-End APV25 hybrids Rad-hard DC/DC converters Analog level translation, data sparsification and hit time reconstruction Unified Belle II DAQ system ~2m copper cable Junction box ~10m copper cable FADC Unified optical data link (>20m) Finesse Transmitter Board (FTB) COPPER

3. Not Entirely New…  2007: plans for an intermediate upgrade of Belle I SVD (inner 2 layers only)  Prototype system built and tested thoroughly in several beam tests since then  Now enlarging and improving details, but concept is same 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics3

4. 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics4 Front-End Junction Box FADC FTB Summary

5. Front-End Electronics  APV25 front-end chip (developed for CMS)  Fast shaping, pipelined, rad-hard, well tested  Two different kinds of readout boards:  Origami chip-on-sensor scheme for center sensors  Conventional PCB hybrids for edge sensors 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics5 Origami PCB hybrid

6. Hybrid Boards & Origami  Edge hybrids designed & tested  Double Origami module built in summer 2012  More about Origami & ladder assembly by Y.Onuki 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics6

7. 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics7 Front-End Junction Box FADC FTB Summary

8. Junction Box 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics8  Rad-hard DC/DC converters instead of regulators  CERN development  Allows to re-use existing PS system

9. DC/DC Converter Noise Measurements  Same noise within measurement precision (few %) between conventional and DC/DC powering! 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics9 Test hybrid (larger) Belle II design (smaller)

10. 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics10 Front-End Junction Box FADC FTB Summary

11. FADC (9U VME module)  Similar to Belle 1 SVD FADC, but with twice higher density (48 APV25 inputs) and more powerful FPGA 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics11

12. FADC Status  FADC Module  Circuit design completed (on paper)  Several circuit details tested already  Analog & digital level translation boards built and tested OK  Now working on translation into CAD and PCB layout  Surrounding components  FADC Controller, Buffer, Backplane  Will be designed after FADC (comparatively trivial)  Firmware development (also based on 2007 prototype) in parallel 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics12

13. 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics13 Front-End Junction Box FADC FTB Summary

14. FTB (DAQ Link)  Porotype board exists  Optical link tests to COPPER at 2.54 and 3.175 Gb/s successful  Second iteration of PCB for minor corrections underway  More on FTB & readout integration by K.Hara 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics14

15. 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics15 Front-End Junction Box FADC FTB Summary

16.  Overall readout scheme  Based on existing (and working) 2007 prototypes  Front-end  APV25 readout with Origami and PCB hybrids  Junction Box  Rad-hard DC/DC converters (no noise penalty)  FADC  Circuit design done, PCB design ongoing  FTB  DAQ link tested successfully with prototype board 1 October 2012M.Friedl (HEPHY Vienna): SVD Readout Electronics16

17. Thank you for your attention. Bad luck for Nadeshiko: Unlike 2011, they only made silver this year… 17