1. SVD Introduction Wetzlar SVD-PXD Meeting, 4 February 2013
Markus Friedl (HEPHY Vienna)

2. Q: What do we have in common with Bob Dylan, David Copperfield, Montserrat Caballé, Deep Purple and Joe Cocker?
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

3. A: They all gave performances in this building – so we are in good company 
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

4. Introduction Front-End Electronics Performance Summary
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

5. Introduction Front-End Electronics Performance Summary
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

6. About 60km northeast of Tokyo
KEKB and KEK ( )
~1 km in diameter
KEKB
Belle
Linac
About 60km northeast of Tokyo
Asymmetric machine: 8 GeV e- on 3.5 GeV e+
Linac
Belle
KEKB
Center of mass energy: Y(4S) (10.58 GeV)
High intensity beams (1.6 A & 1.3 A)
Integrated luminosity of 1 ab-1 recorded in total
Belle mentioned explicitly in 2008 Physics Nobel Prize announcement to Kobayashi and Masukawa
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

7. SuperKEKB/Belle II Upgrade: 2010–2015
Aim: super-high luminosity ~81035 cm-2s-1  11010 BB / year
LoI published in 2004; TDR published in 2010
Refurbishment of accelerator and detector required
nano-beams with cross-sections of ~10 µm x 60 nm
10 mm radius beam pipe at interaction region
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

8. Belle II Vertexing Subdetectors
Silicon Vertex Detector (SVD)
4 layers of DSSDs
Pixel Detector (PXD)
2 layers of DEPFET pixels
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

9. Belle II Vertexing Environment
Low energy machine (10.58 GeV) – multiple scattering
Needs very low mass detector
PXD DEPFET sensors are thinned to 75 µm
SVD uses “Origami chip-on-sensor” concept
High luminosity – occupancy/pile-up
Need small sensitive area and/or fast readout
PXD has small cell size (50 x 50 µm2)
SVD has fast shaping (50 ns) and hit time reconstruction (~3 ns)
Radiation – O(few Mrad)
Magnetic field – 1.8 T
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

10. Silicon Vertex Detector Concept
Use largest possible (6”) double-sided sensors (DSSDs)
Minimize relative amount of structural material
Fast shaping readout
Minimize occupancy
Fast readout implies higher noise
Noise is mainly determined by input capacitance
Place readout chips as close as possible to sensor strips
Minimize capacitive load by avoiding long fanouts
Use efficient CO2 cooling
Allows thin cooling pipes
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

11. Belle II Vertex Detector
Pixel Detector
2 DEPFET layers at r = 14, 22 mm
Excellent and unambiguous spatial resolution (~15 µm)
Coarse time resolution (20 µs)
Silicon Vertex Detector
4 DSSD layers at r = 38, 80, 104, 135 mm
Good spatial resolution (~25 µm) but ambiguities due to ghosting
Excellent time resolution (~3 ns)
Combining both parts yields a very powerful device!
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

12. Introduction Front-End Electronics Performance Summary
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

13. Front-End Geometry 4 layers arranged in ladders
Outer 3 layers have slanted forward part
Limited acceptance angle (17°…150°) allows to place services outside (cyan cones) while minimizing material within
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

14. Double-Sided Silicon Sensors
3 different types required
Large rectangular sensors – 123 x 58 mm2 (HPK)
Small rectangular sensors – 123 x 38 mm2 (HPK)
Trapezoidal sensors – 123 x 58…38 mm2 (Micron)
Production is in progress
Presently ~60% delivered
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

15. Origami Chip-on-Sensor Concept
Low-mass double-sided readout
Flex fanout pieces wrapped to opposite side
All chips aligned on one side  single cooling pipe (D = 1.6 mm)
Side View (below)
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

16. Origami Prototype Modules
Single Origami module
Double Origami module
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

17. Sensor underneath flex circuit
APV25 chips
Cooling pipe
Origami ladder
Sensor underneath flex circuit
Pitch adapter bent around sensor edge
End ring (support)
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

18. Introduction Front-End Electronics Performance Summary
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

19. General SVD Readout Scheme
Based on existing prototype system (2007) verified in lab and beam tests
DATCON
ONSEN
1748 APV25 chips
Front-end hybrids
Rad-hard DC/DC converters
Analog level translation, data sparsification and hit time reconstruction
Unified Belle II DAQ system
~2m copper cable
Junction box
~10m copper
cable
FADC
Unified optical data link (>20m)
Finesse Transmitter
Board (FTB)
COPPER
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

20. APV25 Front-End Chip Developed for CMS by IC London and RAL
70,000 chips running in the CMS Tracker since 2008
40 MHz clock; 128 channels; 192 cells deep analog pipeline
50 ns (adjustable) shaping time
0.25 µm CMOS process (>100 MRad tolerant)
Low noise: 250 e + 36 e/pF
Multi-peak mode (read out several samples along shaping curve)
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

21. Junction Box CERN-made DC/DC converters for front-end powering
Comparative measurement: no noise penalty
M.Friedl (HEPHY Vienna):SVD Readout Status
21 January 2013

22. FADC Block Diagram
Analog & digital level translation between  bias and GND
Digitization, signal conditioning (FIR filter), data processing
Central FPGA is an Altera Stratix IV GX
M.Friedl (HEPHY Vienna):SVD Readout Status
21 January 2013

23. FADC: Overall Concept
9U VME module (needs much space for level translation circuits)
Circuit is designed, now PCB layout is made
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

24. FTB: Link to DAQ and PXD Firmware development ongoing
Optical link tests at 2.54 and Gb/s successful
Second iteration of PCB for minor corrections underway
SVD data are also streamed to PXD for online data reduction
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

25. Introduction Front-End Electronics Performance Summary
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

26. Hit Time Reconstruction Benefits
Belle I SVD
Belle II SVD
Sufficient to cope with a 40-fold increase in luminosity
M.Friedl: Belle II SVD
18 October 2012

27. Achieved Hit Time Resolution
Results achieved in beam tests with several different types of Belle II prototype modules (covering a broad range of SNR)
2...3 ns RMS accuracy at typical cluster SNR ( )
Will be done in FPGA (using lookup tables) – simulation successful
Close to theoretical limit
(G. De Geronimo, in “Medical Imaging” by K. Iniewski)
M.Friedl: Belle II SVD
18 October 2012

28. Z Vertex Resolution
Belle II (PXD & SVD) will be a factor 2 better than Belle (SVD only)
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

29. Introduction Front-End Electronics Performance Summary
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013

30. Summary Belle II Vertex Detector consists of Silicon Vertex Detector
Pixel Detector (PXD): unambiguous spatial resolution
Silicon Vertex Detector (SVD): precise timing
Silicon Vertex Detector
4 layers of 6” double-sided silicon sensors
APV25 front-end chip with 50 ns shaping time
Origami chip-on-sensor readout concept for low mass
Highly efficient CO2 cooling
R&D completed, construction has started
Now building final prototypes
M.Friedl (HEPHY Vienna): SVD Introduction
4 February 2013