Token Bit Manager for the CMS Pixel Readout Edward Bartz (R.Stone) Rutgers University Description of the TBM Functions First Prototype in DMILL 0.25 m Translation CMS Pixel Electronics Systems Review 5 November 2003

 Custom, Mixed Mode, Rad-Hard, Chip Located Near Pixel Readout Chips TBM Overview Orchestrate the Readout of Several Pixel Chips on a Single Analog Output Link Provide a Link Between the Front End Controller and the Pixel Chips For Control Commands  Custom, Mixed Mode, Rad-Hard, Chip Located Near Pixel Readout Chips

Dual TBM Chip Dual TBM Chip Dual HUB TBM Chain of Read Out Chips Control Commands 40 MHz Clock CLK L1 Analog Output L1A Dual TBM Chip Two Token Bit Manager’s Each TBM Controls one ROC Chain 8 to 24 ROCs per TBM Control Network Hub Port addressing for control commands 6 to 14 Dual TBMs per Control Link 120 Links in the Detector ~1200 TBMs & 20,000 ROCs

TBM Functions Write header and trailer (2 bit analog encoded digital) 8 bit Event Number  Header 8 bit Error status word  Trailer Distribute to Pixel Readout Chips (ROC) L1 triggers (2 Outputs/TBM) Clock (2 Outputs/TBM) Control readout through token pass Stack triggers awaiting token pass 32 event deep No readout after 16 deep L1 Trigger TBM ROC CLK Token In Token Out Analog Output Analog Output Clock Reset To Flash ADC

Analog Output Levels Chosen To Match ROC Output Levels Fully Adjustable Gain Adjustment Differential Offset Adjustment Driver Current Adjustment Output Driver Identical to ROC Note: Voltages are referenced to Analog Optical Link input. Levels 4&5 ROC Only

TBM Control Features Analog Adjustments Trigger Control Token Passing Adjust Analog Levels Disable Analog Output Trigger Control Inject Any Trigger Type Ignore Incoming Triggers Disable Trigger Outputs Token Passing Disable Token Passing Reset Token Out Stack Control Read Number of Events on Stack Read Stack Contents (non-destructively) General Control Switch Readout to 40 MHz or 20 MHz Disable TBM Clock Reset TBM

Control Network Hub Dual TBM HUB TBM ROC Up to 32 hubs addressable. mI2C 4 mI2C Ports Output Only Control Link ROC Up to 32 hubs addressable. 5 Ports per hub. 4 mI2C (40 MHz) external  ROCs. 1 mI2C (40 MHz) internal  TBMs. Functions of addressed hub. Selects addressed port. Strips off byte containing hub/port address. Passes remainder. Reflects data back to Front End Controller.

DMILL Dual TBM 4 mm 5.3 mm 1st (& only) Sub. 5/02 It Works! Analog sections Stacks Control sections Hub 5.3 mm 4 mm 1st (& only) Sub. 5/02 It Works!

TBM Test Results Trailer ID Header ID 6 Tested / 5 Fully Functional Event # = 11 Status Reg. UBLK 1 2 3 Trailer ID Header ID Token Pass Power consumption 600 mW core 140 mW Differential Drivers 460 mW 6 Tested / 5 Fully Functional Header marker 3 “UBLK” + “1” 8 Bit Event Number (4 Clocks) Trailer marker 2 “UBLK” + 2 “1” 8 Bit Status Word (4 Clocks)

Analog Adjustability Before Adjustment After TBM 1 TBM 2

Expected Max CMS Trigger Rate = 100KHz 1 MHz Trigger Rate Expected Max CMS Trigger Rate = 100KHz Header ID Event Number Status Info Trailer ID

mI2C Command Output From Port 0 Hub Testing Internal fast port - fully tested and functional External fast ports - fully tested and functional mI2C Command Output From Port 0 Serial Data Serial Clock

Changes For 0.25 m Reduce Power Consumption Limit use of Analog bus Redesign LVDS Drivers Minimize Clock Usage Shut Down Clock when not needed Limit use of Analog bus Pass ROC Analog Through TBM Analog Output Line Driver Redesign Serial Protocol For CMS Optical Transceivers. 8 Bit data + Complement Bit 8  4 Bit data + Complement Bit 4 Request Modification to Optical Receiver Chip Allow Transition Dual  Single TBM Operation

TBM Operation Modes Dual Mode Single Mode S ROCs ROC readout Readout token chip 1-8 Half-Module Readout 1 S Readout token chip 9-16 Half-Module Readout 2 Dual Mode ROCs S ROC readout Readout token Module Readout Single Mode TBM

Single Event Upset SEU cross section of 0.25mm Flipflop [cm2] SEU cross section of 0.25mm Flipflop 300 MeV/c pion beam Standard: s =2 x 10-13 cm2 Protected: s =2 x 10-15 cm2 (284 ff per DTBM) 10-12 10-13 10-14 10-15 TBM Placement Expected Flux (MHz/cm2) Time Per SEU Protected F/F (Hrs/SEU) 4cm Barrel 40 12 7cm Barrel 20 24 11cm Barrel/ Foreward 8 60 10-16 10-17 1.4 1.6 1.8 2.0 2.2 2.4 2.6 Standard Latch Protected Latch

0.25 m Hub “Fast” Hub “Slow” Hub IBM Process “Fast” Hub “Slow” Hub 3 metal layers MIMCaps “Fast” Hub Normally Part of TBM Tested in Simulation with ROC Control Section PSI Low Power LVDS Drivers “Slow” Hub Can reside on same control link as Fast hubs Provides Control data for PLL & Laser Drivers Via I2c Protocol Submitted June 2003 Received: Sept. 19, 2003 “Fast” Hub “Slow” Hub

Slow Hub Modified Version of Fast Hub Divide 1 to 7 By 256 Decoder Serial Data In 40 MHz Clock Slow Clock Out Start-Stop 8 Bit Reg. Address Compare 1 to 7 Decoder 7 to 1 Mux Divide By 256 Odd Data Bits Slow Data I/O Return Modifications

0.25 m Dual TBM IBM Process 3 voltage regulators 4.4 mm 3.2 mm 3 metal layers MIMCaps 3 voltage regulators Core Digital Analog LVDS Drivers Pad Dominated Completed: October 2003 CERN rules check now Nov 10th MPW submission Analog Readout Analog Power Stacks Control Sections 4.4 mm Hub Regulators 3.2 mm

2nd 0.25 m Version Fix any bugs? Improvements Spring 2004 submission? Rad-Hard regulator band gap reference More flexibility in token passing (bypass non-responding ROC segment) TBM Aout driver enhancements Spring 2004 submission? Analog Readout Analog Power Stacks Control Sections Hub Regulators

Conclusion Dual TBM worked on first DMILL submission 0.25 m Fast and Slow Hubs are Awaiting Testing 0.25 m TBM Complete 10 November 2003 MPW Submission Second 0.25 m Prototype Submission Anticipated Production TBM Available End of 2004