1. CCU25 Communication and Control Unit ASIC in CMOS 0.25 μm Ch.Paillard
LECC 2002
COLMAR
Ch.Paillard CERN EP

2. SUMMARY CMS tracker slow control Network architecture and redundancy
Messages structure
CCU25 Bloc diagram
Detail of Blocs I2C, parallel, memory, jtag, trigger
Radiation hardness and irradiation test
Conclusions
I will first present to you an overall view of the CMS tracker slow control system
then the network architecture and redundancy
The format of the messages in the network ring
The bloc diagram of the CCU25
A detailed description of each internal bloc of the ccu an their (theur) functions
The radiation hardness feature and the result of irradiation test
And conclusions.
LECC 2002
COLMAR
Ch.Paillard CERN EP

3. Tracker slow control FED Front-end Module FEC CCUM to DAQ Data PathLD
Det
APVs to
DAQ
A/D
Memory I V
A/D
DCU
PLL-Delay
Temp
FED
Front-end
Module
TTCrx
Data
Path
I2C
CLK & T1
Control
Path
LVDSMUX
CLK - T1
TTCrx
Here is the block diagram of the whole tracker with the data path and the control path
In the CMS tracker slow control, the fec (front-end controller)is outside the detector meters far from the beam
Digital optical link The first 100 meters of the path are covered by optical fiber
Here is the optical to electric converter, in the tracker
And the ccu chips connected to f-e
The ccu is in the control path with the FEC.
The right part is in the control room protected from radiations , the left part is in the detector near the beam.
Only one ccu is here represented but they will be about 10 connected in each FEC
The higher part is the data path with the front-end chip connected to the silicium detector
LVDS
BUF
CCU
FEC ctrl
PCI
Intfc
FEC
CCUM
On detector
In control room
LECC 2002
COLMAR
Ch.Paillard CERN EP

4. RING Trigger LECC 2002 COLMAR Ch.Paillard CERN EP
Internal protocol
Trigger
FEC
CCU
CCU
CCU
User accessible protocol:
I2C, Memory, Parallel, JTAG
Application
ASICs
Application
ASICs
Application
ASICs
This schema explains how the ccus of the precedent figure are connected.
They are organized in a ring network.
The network architecture is a ring made up of a master (FEC) and 1 or several CCU.
The Fec is the master of the ring and it is made of a PMC card plugged in a processor controlling the ring from outside the detector
The timing is also transmitted by the network.
The F-E chip are connected to the interface parts of the ccu.
And The protocol in the ring is a protocol like "Token Ring IBM” at 40 Mbit/s
Between the CCU and the external circuit , one of the different protocols available on the ccu is used. I2c,Memory.Parallel or JTAG
LECC 2002
COLMAR
Ch.Paillard CERN EP

5. Network architecture Channel protocol Ring protocol (Token-Ring)
FEC-CCU (Front End Controller)
CCU-CCU
Message-based
Broadcast
Write = post
Read request
Request packet
Channel protocol
CCU-Channels
I2C, Jtag, Memory
Parallel
Data part
Channel specific
Asynchronous
concurrent
The network architecture is composed of Two layer; the ring protocol and the channel protocol
The first layer (ring) connects the Front End Controller (FEC) to the CCU and the CCUs between themselves.
The ring layer uses a protocol similar to a Token Ring local area network protocol and is
Message based
The second layer is the channel protocol .
It is used between CCU and Channel only to send and receive data from the different types of interfaces of the CCU.
So This is the data part of the message
This second layer is specific to the channels.
For example : the protocol is not the same for a channel memory and for an I2C channel.
The operation is asynchronous and
The channels are able to work concurrently.
Broadcast is supported
Writing is simply posting a write operation to the channel
For read operation a read request is sent to the channel
then the channel perform the operation and return a message containing the read value.
We find the same partition as in the network.
To know: a layer calls ring for the communication between FEC and CCU and CCU, and a layer call channel for the communication between the ccu and the external modules.
LECC 2002
COLMAR
Ch.Paillard CERN EP

6. Messages format SOF EOF TOKEN SOF Destination Source Length Data
CRC-16
EOF
CH#
TR#
Channel Specific command
CH#
TR#
CMD
ADDR
Data
I2C write
the Token indicates that the network is in idle state.
It Is made of two special symbol: (start of frame) sof and (end of frame)eof
This line represents the format of the messages circulating in the ring
SOF Destination (this is the address of ccu to which the message is sent) – source (this is the address of the master FEC)
length of message
The data part
Cyclic redundancy check (Crc-16) and End oF Frame
In the data part we find the channel number , the transaction number and the command which is specific to the channel.
The transaction number identifies the operation.
The last line is an example of write transaction on i2c channel with the command the address of i2c device and the data byte
LECC 2002
COLMAR
Ch.Paillard CERN EP

7. FUNCTIONS of CCU Communication Control Link between CCU & FEC
Token Ring network
2 line data and clock
Data line NRZI
Timing transport
In clock line
7-bit address => 127 ccu in ring
Control
Link between CCU & F-E chips
Several protocol
16 I2C master
1 JTAG master
1 memory
4 parallel interfaces
There are 2 main functions in the CCU, a communication part and a control part.
The communication function establish link between CCU and FEC
Each CCU has an 7-bit address therefore we can connect hundred and twenty seven CCU in a ring.
The communication part is the first layer of the communication architecture, and is responsible for the transfer between FEC and CCU and between CCU.
The control layer is here to transport datas between CCU and external circuits.
In the communication function the transport of trigger is also included
LECC 2002
COLMAR
Ch.Paillard CERN EP

8. CCU25 Block diagram JTAG Master JTAG Slave Alarms Trigger Decoder
Interrupts[0-3]*
JTAG
Master
JTAG
Slave
Alarms
ST1
Trigger
Decoder
CLKI(A)
Clock
Distribution
ST2
ST3
CLKI(B)
ST4
Trigger Counter
& other timing logic
CLKO(A)
DO(A)
Reset*
Node Controller
Link
Controller
DI(A)
CLKO(B)
DO(B)
SCL
SDATA
I2C Master
DI(B)
16 x I2C Buses
Memory Bus
Interface
Ext Reset*
Here is the block diagram of the CCU25.
You can recognize the various parts mentioned before.
The interface network lies on the right-hand side with the 2 inputs and 2 outputs for the 2 redundant rings.
In the centre you can see the node controller which is used as interface between the network and the various channels.
All different channels are connected by an internal bus in the node controller.
There are sixteen interfaces I2C.
memory
Here 4 interfaces parallell with eight bit individually programmable to input or output
and the block of trigger decoder
Parallel interface
I2C Master
D[0:7] A[0:15] R/W CS[1-2]*
PA[0:7] PB[0:7] PC[0:7] PD[0:7]
Local Bus
LECC 2002
COLMAR
Ch.Paillard CERN EP

9. Node Controller Control network & channels Control Register (5)
Select net Input A-B
Select Output A-B
Enable channels
Reset channel
Alarm
External reset out
Status register (6)
Illegal sequence
Crc error
Invalid command
I2C busy
Parity error counter
Transaction number
This bloc is the central part of the CCU.
The principal function of this block is the control of the network interface and the supervision of the internal channels.
It contains different control and status registers
There are five control registers
This is an overview of some bits present in this control registers.
One bit for selecting the network input
One for selecting the network output
Bits to enable the channels pas un verbe
Reset channels
Alarm setting
And external reset output
There are 6 status registers
Bit for illegal sequence of symbol on the network
Ono bit Crc error
Reception of an invalid command
Sixteen bits indicating a busy I2C channel
Parity counter and last transaction number is available
===============================
The node controller is controlling the setting of the network interface and the setup of the different channels. Enable-disable channel , reset channel
This block contains the status registers indicating the state and the error having taken place on the network.
Some other registers command effect of alarm and external reset.
Broadcast class this is a register commanding the effect of broadcast command. 1min
LECC 2002
COLMAR
Ch.Paillard CERN EP

10. I2C Interface 2 wires clock, data Read-write Read-mod-Write
7-bit addr, 8-bit data
10-bit addr, 8-bit data
APV6 mode
Read-mod-Write
and, or, xor
Status registers
Detection of line data low
Invalid command
Transaction last succ.
Transaction last bad
Last command
Control register
Clock freq. 100,200,400,1000 Khz
Write acknowledgement or not
mask
This interface is a master I2C having several operating mode.
The I2C Bus consists of 2 wires: 1 for the clock and a bi-directional for the data.
The clock frequency is programmable between 100 Khz and 1 MHz.
There are Several modes of transfer :
Read-write in 7-bit address and 8 bit data
Read-write in 10 bit address and 8 bit data EXTENDED
Special mode for APV6 front end modules
Read-modify-write with and, or, xor operation
Status register containing
State of the i2c data line
A bit indicating if this bloc as receive invalid command
The transaction number of the last successful command
The transaction number of the last unsuccessful command
the code of the last command executed
And a control register to program the clock frequency between hundred khz and 1 mega hertz
A mask register for read-mod-write operation
LECC 2002
COLMAR
Ch.Paillard CERN EP

11. Memory Interface 16-bit addr., 8-bit data 2 windows pre-decoded
Block transfer
Read mod. write
and, or, xor
Status registers
Inv. Command
Inv. Address
Control registers
Length chip select
Windows 1 & 2
Enable w1 et w2
This interface is designed like an interface of bus 8 bits microprocessor which can address memory device or other similar devices (Dac-adc...).
The address is 16 bits wide and the data 8 bits
2 decoded outputs in 2 programmable windows are provided
Block transfer are possible
Read modify write cycle in and or exclusive or operation
Status registers
containing bit for invalid command
invalid address
Control registers
The low address and the high address of the 2 windows
And enable bit for this 2 windows
LECC 2002
COLMAR
Ch.Paillard CERN EP

12. Parallel Interface 8-bit bi-dir Input strobe Output strobe
Each bit individually
Input strobe
Tr ou level
interrupt
Output strobe
100ns,200ns,400ns,1μs
Status registers
Interrupt
Inv. Command
Control registers
Strobe 100,200,500,1000 ns
Enable interrupt
This interface contains 8 bit individually programmable for input or output
It has also one input strobe and one output strobe .
The length of the output strobe is between hundred ns and 1 micro-second programmable.
We can program the input strobe to be sensible to a transition or a level
This interface can generate interrupts to the FEC (tr=0) from the input strobe
The bits of status register show the status of interrupt and if an invalid command occurred to this interface.
Control
One ccu25 contains four blocks of this type.
LECC 2002
COLMAR
Ch.Paillard CERN EP

13. JTAG MASTER Simplified JTAG master No command structure
TCK, TMS, TDO out, TDI in
No command structure
Need special ring packet
Example of data part message
This is a simplified JTAG master
There is not command structure and the JTAG protocol is generated by the FEC.
Each byte of the data part of the ring message contain four TMS bit and four TDO bit,
For each data byte 4 clocks TCK are generated by the CCU. .
TMS[11:8]
TDO[11:8]
TMS[7:4]
TDO[7:4]
TMS[3:0]
TDO[3:0]
LECC 2002
COLMAR
Ch.Paillard CERN EP

14. Trigger Distribution of ST1-ST4
ST1- ST4 output can be delayed (1-16) clock period
4 Counters 32-bit
2 LVDS input T1 and Clock
~ 25 ns
CLK
The function of this bloc is to decode special trigger signals (T1-T4)
The T1 signal is the level 1 trigger of the experiment
It has outputs for this 4 signals and each signal can be delayed from 1 to 16 clock period
Four 32 bit counters are present to accumulate and compare the number of received trigger with other module of the detector.
The trigger signals are transmitted in the clock line of the network in this form T1
CLK+T1
LECC 2002
COLMAR
Ch.Paillard CERN EP

15. Redundancy LECC 2002 COLMAR Ch.Paillard CERN EP
Here is the scheme for redundancy, the FEC is not represented here.
The primary ring passes from one ccu to the next directly, the secondary ring jump for CCU 1 to the CCU 3 and so one
If a ccu fail, this architecture support an alternative path going around the faulty node which allow to keep the ring functioning.
If the ccu three is faulty, then the messages take this way.
The digital optical links are also redundant.
LECC 2002
COLMAR
Ch.Paillard CERN EP

16. Radiation–Hardness and irradiation
For total dose tolerance
Library of standard cells rad-tolerant μm CMOS
For SEU robustness
One-hot type state machine
Node controller 3 blocks + majority voting
Parity on all registers
Error counter
Irradiation:
Test at PSI 300 MeV proton beam 3x108 p/s
4.5 SEU/chip/hour => LHC 4.21x10-2 SEU/chip/hour
For total dose tolerance
The CCU25 has been fabricated with a rad-tolerant library in 0.25 um CMOS .
For SEU robustness
All state machines are of one-hot type.
The network and node controller are replicated 3 time and its output signals are selected after a majority voting circuit
which takes as valid output the signal for which at leat 2 of the three blocks agree.
Parity bit are present on each registers.
And error counter for monitoring SEU events.
We irradiated sixteen CCU in a 300 Mev proton beam
We detected 4.5 single event upset (SEU) by chip and by hour
And extrapolation give 4.21 x 10-2 SEU by chip by hour in worst case position at LHC
LECC 2002
COLMAR
Ch.Paillard CERN EP

17. CCU_M photo LECC 2002 COLMAR Ch.Paillard CERN EP
Here you can see the CCU25 mounted on the CCU_M module
Here is the schematic of this module with the LVDS drivers for the electrical connection of the ring in the detector.
LECC 2002
COLMAR
Ch.Paillard CERN EP

18. CCU25 layout Synthesis from HDL Features 6x6 mm2, 3 metals
196 pin fpBGA
array 14x14 with 1mm pitch v
This is the layout of CCU in 0.25 um technology entirely.
Six by six square millimeters
One hundred and ninety six I/o pin and is packaged in a BGA
Its power consumption is Two hundred fifty mili-watt at 2.5 volt
That is a view of the package which measure fourteen by fourteen millimeters
LECC 2002
COLMAR
Ch.Paillard CERN EP

19. CONCLUSIONS Network interface (Like Token Ring) 40 Mb/s
Control interface
I2C, parallel, memory bus and JTAG.
Radiation resistant
To conclude
The ccu25 contains a network interface at 40 MB/s and control interface for
I2c bus, parallel interface for switch , memory bus type for connection of ADC or dac or….. And JTAG interface .
It is radiation resistant.
It will be use for the slow control of CMS tracker and other part of the CMS experiment.
LECC 2002
COLMAR
Ch.Paillard CERN EP