The Belle II Silicon Vertex Detector Markus Friedl (HEPHY Vienna) for the Belle II SVD Group VCI, 13 February 2013

13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD2 Introduction Front-End Electronics Performance Summary

13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD3 Introduction Front-End Electronics Performance Summary

KEKB and KEK ( )  Center of mass energy: Y(4S) (10.58 GeV)  High intensity beams (1.6 A & 1.3 A)  Integrated luminosity of 1 ab -1 recorded in total  Belle mentioned explicitly in 2008 Physics Nobel Prize announcement to Kobayashi and Masukawa Linac Belle KEKB ~1 km in diameter KEKB Belle Linac About 60km northeast of Tokyo  Asymmetric machine: 8 GeV e - on 3.5 GeV e + 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD4

SuperKEKB/Belle II Upgrade: 2010–2015  Aim: super-high luminosity ~8  cm -2 s -1  1  BB / year  LoI published in 2004; TDR published in 2010  Refurbishment of accelerator and detector required  nano-beams with cross-sections of ~10 µm x 60 nm  10 mm radius beam pipe at interaction region 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD5

Belle II Vertexing Subdetectors 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD6 Silicon Vertex Detector (SVD) 4 layers of DSSDs Pixel Detector (PXD) 2 layers of DEPFET pixels

Belle II Vertexing Environment  Low energy machine (10.58 GeV) – multiple scattering  Needs very low mass detector  PXD DEPFET sensors are thinned to 75 µm  SVD uses “Origami chip-on-sensor” concept  High luminosity – occupancy/pile-up  Need small sensitive area and/or fast readout  PXD has small cell size (50 x 50 µm 2 )  SVD has fast shaping (50 ns) and hit time reconstruction (~3 ns)  Radiation –  100 kGy  Magnetic field – 1.8 T 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD7

Silicon Vertex Detector Concept  Use largest possible (6”) double-sided sensors (DSSDs)  Minimize relative amount of structural material  Fast shaping readout  Minimize occupancy  Fast readout implies higher noise  Noise is mainly determined by input capacitance  Place readout chips as close as possible to sensor strips  Minimize capacitive load by avoiding long fanouts  Use efficient CO2 cooling  Allows thin cooling pipes 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD8

Belle II Vertex Detector  Pixel Detector – 8M pixels  2 DEPFET layers at r = 14, 22 mm  Excellent and unambiguous spatial resolution (~15 µm)  Coarse time resolution (20 µs)  Silicon Vertex Detector – 220k strips  4 DSSD layers at r = 38, 80, 104, 135 mm  Good spatial resolution (~12/25 µm) but ambiguities due to ghosting  Excellent time resolution (~3 ns)  Combining both parts yields a very powerful device! 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD9

13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD10 Introduction Front-End Electronics Performance Summary

Front-End Geometry  4 layers arranged in ladders  Outer 3 layers have slanted forward part  Limited acceptance angle (17°…150°) allows to place services outside (cyan cones) while minimizing material within 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD11

Double-Sided Silicon Sensors  3 different types required  Large rectangular sensors – 123 x 58 mm 2 (HPK)  Small rectangular sensors – 123 x 38 mm 2 (HPK)  Trapezoidal sensors – 123 x 58…38 mm 2 (Micron)  Production is in progress  Presently ~60% delivered 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD12

Origami Chip-on-Sensor Concept  Low-mass double-sided readout  Flex fanout pieces wrapped to opposite side  All chips aligned on one side  single cooling pipe (D = 1.6 mm) 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD13 Side View (below)

Origami Prototype Modules  Single Origami module  Double Origami module 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD14

13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD15 APV25 chips Cooling pipe Origami ladder Sensor underneath flex circuit Pitch adapter bent around sensor edge End ring (support)

13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD16 Introduction Front-End Electronics Performance Summary

General SVD Readout Scheme  Based on existing prototype system (2007) verified in lab and beam tests 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD APV25 chips Front-end hybrids Rad-hard DC/DC converters Analog level translation, data sparsification and hit time reconstruction Unified Belle II DAQ system ~2m copper cable Junction box ~10m copper cable FADC Unified optical data link (>20m) Finesse Transmitter Board (FTB) COPPER DATCONONSEN

APV25 Front-End Chip  Developed for CMS by IC London and RAL  70,000 chips running in the CMS Tracker since 2008  40 MHz clock; 128 channels; 192 cells deep analog pipeline  50 ns (adjustable) shaping time  0.25 µm CMOS process (>100 MRad tolerant)  Low noise: 250 e + 36 e/pF  Multi-peak mode (read out several samples along shaping curve) 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD18

Junction Box 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD19  CERN-made DC/DC converters for front-end powering  Comparative measurement: no noise penalty

FADC Block Diagram  Analog & digital level translation between  bias and GND  Digitization, signal conditioning (FIR filter), data processing  Central FPGA is an Altera Stratix IV GX 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD20

FADC: Overall Concept  9U VME module (needs much space for level translation circuits)  Circuit is designed, now PCB layout is made 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD21

The “Human” Touch… 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD22

FTB: Link to DAQ and PXD  Firmware development ongoing  Optical link tests at 2.54 and Gb/s successful  Second iteration of PCB for minor corrections underway  SVD data are also streamed to PXD for online data reduction 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD23

13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD24 Introduction Front-End Electronics Performance Summary

Hit Time Reconstruction Benefits  Sufficient to cope with a 40-fold increase in luminosity 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD25 Belle I SVD Belle II SVD

Achieved Hit Time Resolution 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD26  Results achieved in beam tests with several different types of Belle II prototype modules (covering a broad range of SNR)  ns RMS accuracy at typical cluster SNR ( )  Will be done in FPGA (using lookup tables) – simulation successful Close to theoretical limit (G. De Geronimo, in “Medical Imaging” by K. Iniewski)

Z Vertex Resolution  Belle II (PXD & SVD) will be a factor 2 better than Belle (SVD only) 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD27

13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD28 Introduction Front-End Electronics Performance Summary

 Belle II Vertex Detector consists of  Pixel Detector (PXD): unambiguous spatial resolution  Silicon Vertex Detector (SVD): precise timing  Silicon Vertex Detector  4 layers of 6” double-sided silicon sensors  APV25 front-end chip with 50 ns shaping time  Origami chip-on-sensor readout concept for low mass  Highly efficient CO2 cooling  Schedule  R&D completed, construction has started  Now building final prototypes (pre-series) 13 February 2013M.Friedl (Belle II SVD Group): The Belle II SVD29