1. The Silicon Vertex Detector of the Belle-II Experiment
Tomoko Iwashita-Morii
University of Tokyo, KAVLI IPMU
On behalf of the Belle-II SVD Group
Delivered by
Francesco Forti
University and INFN, Pisa
May 28th, 2015
The 13th Pisa Meeting

2. The Belle II Experiment
Belle II is an e⁺-e⁻ collider experiment with √s̄ ≈ mΥ(4S).
Target luminosity is L = 8.0 x 10³⁵/cm²s.
New physics search beyond the SM in Belle II
CP-violating parameters in various B-decay modes will isolate a NP model out of the several hypotheses.
b → sqq̄, b → cc̄s, B⁰ → KS⁰π⁰γ, B⁰ → KS⁰KS⁰KS⁰, …
The B-decay vertex is essential information to access to the parameters.
Belle II detector
KEK, Japan e⁻ e⁺

3. Belle II Vertex Detectors
See Poster by L.Vitale:Belle-II VXD radiation monitoring and beam abort with scCVD diamond sensors.
Belle II Vertex Detectors
PiXel Detector (PXD)
The inner most detector comprised of DEPFET pixels.
Silicon Vertex Detector (SVD)
Next inner detector to the PXD comprised of double-sided strip detectors of silicon.
SVD
Track impact parameter resolution: σd₀ [mm]
σd₀ ~ 40μm @ pT = 2GeV/c
PXD
Two vertex detectors are installed at the Belle II center.
pT [GeV/c]

4. The PiXel Detector (PXD)
Depleted p-channel FET
Fully depleted → large signal, fast signal collection.
Low capacitance, internal amplification → low noise.
Collected q in the internal gate is digitized only when the FET is on → low power consumption.
Readout ASIC functions
FET array switcher
Drain current digitizer
Data handler (zero suppression)
Monolithic silicon sensor
Two-layer structure
Thickness = 75μm
# of pixel = 768 x 256
Pixel size ~50 x 55µm²
100ns / 250 pixels
S/N > 17
30 wafers has been produced so far.
Layer
Radius L1
14mm L2
22mm

5. SVD Structure L6 L5 L4 L3 SVD cut model Layer structure Four layers
# of ladders L6 16 L5 12 L4 10 L3 7
SVD cut model
Four layers
Layer structure
RL3 = 38mm
RL4 = 80mm
RL5 = 115mm
RL6 = 140mm
~650mm L6 L5 L4 L3
Sensor
Trapezoidal sensor
Sensor
Rectangular sensor
Angular acceptance 17⁰<θ<150⁰
Forward
In order to have a better vertex resolution and KS⁰ reconstruction efficiency, the outer SVD radius is doubled w.r.t. the Belle SVD.
The traditional cylindrical shape detector demands many sensors.
The Belle II SVD is designed with a lantern shape.
Sensors have an alignment mark “F” at its four corners.

6. SVD Sensors and Readout ASIC
Double-sided Si strip detector
Readout ASIC (APV25)
Since a high hit rate is anticipated in Belle II, a readout chip should have a short signal shaping time for low noise and a good radiation hardness.
P⁺ strip
Sensor thickness = μm Si
We adopted the APV25
“DSSD”
N⁺ strip
The APV25 was originally developed for the CMS.
Shaping time = 50ns.
Radiation hardness > 1MGy.
Other characteristics
# of input channels = 128 / chip.
192-deep analog pipeline for the dead-time reduction.
Thinned to 100μm for the material budget reduction.
Rectangular
Trapezoidal
# of p-strips
768
p-strip pitch
75μm
50…75μm
# of n-strips
512
n-strip pitch
240μm
Active area
57.72x122.9mm²
5890 mm²

7. Chip-on-Sensor and “Origami” Concepts
APV25 on the sensor
An APV25, reading out a sensor, is placed on the sensor to minimize the analog path length for the capacitive noise reduction.
Sensor backside readout
Signals on the sensor backside are transferred to the sensor front side by other flex circuits and readout by APV25 chips mounted on the front side.
… …
DSSD n-side (512 strips)
Signal readout by the APV25s on the sensor
Backside signal readout by the other APV25s
Fan-out flex circuit
Wire bonding between the sensor and flex
The other flex
Readout ASICs on the same side & same line → easier chilling by a single cooling pipe.

8. Snapshot – the “Origami” Concept
DSSD backside
Flex
APV25
DSSD
The backside signals are transmitted to the APV25 via bent (and glued) flex circuits.
DSSD front side with APV25s

9. Precision DSSD alignment
SVD Ladder Assembly
Sensor fixed on a jig
Sensor placement
DSSDs are handled with precision assembly jigs (O(50μm)), on which the sensors are fixed by vacuum chucking.
Sensors are aligned in O(10μm) by a position tuning jig with monitoring through a CMM.
Precision DSSD alignment
Flex circuit hybrid
APV25
Thermal insulator
Thermal insulator
APV25
DSSD array
Flex circuits
APV25
Support ribs

10. See Poster by V.Babu: Belle-II SVD ladder assembly procedures
Ladder fabrication: gluing
Electrical connection: wire bonding
Ladders are fabricated by gluing the components by Araldite®2011.
The flex↔DSSD strips and flex↔APV25s are electrically connected by the wire bonding
Glue spread below bonding pads affects to the bonding yield and pull strength → glue amount and glue lining are controlled by a gluing robot.
with Aℓ(99%) wire(φ=25μm). Number of total bonds = 450k.
Bonding machine parameters are so tuned to realize yield>99% and pull strength f: μf>5gw, σf/f<20%.
Appropriate spread of glue to the flex edge
Wire bonding pads
μf = 10.7gw
σf = 0.6gw
(97 samples)
t = 55+10μm
Entries / 0.5gw
Glue thickness [μm]
Position on the gluing line [mm]
Pull strength [gw]

11. Electrically Full Functioning Ladder
L5 ladders
Mechanical mockup ladder
The first electrically full functioning ladder completed in Apr. 2015
Sensor displacement is measured by the CMM.
All sensor displacement are found <160μm from the design.
The ladder assembly procedure has been consistently established with achieving a good sensor placement precision.

12. Electrical Performance Studies
Study on the full functioning ladder
Study on a single sensor
Ladder cross-section
Cluster charge
The ladder is bombarded by β-rays from ⁹⁰Sr (12.3MBq).
Shades by the support ribs are clearly observed in the hit maps.
Correlation between p- and n-charge is obvious.
Support ribs
Cluster charge (p-side) [e]
Hit maps
FWD rectangular
Cluster charge (n-side) [e]
P-side cluster charge (#strip≥2)
Central rectangular
μ~23,000e
All studies so far indicate good performance.
BWD rectangular
The distribution(blue) well fits to the Landau(red).
x10³
Cluster charge [e]

13. PXD region of interest gen
SVD Readout Backend
“COPPER” board RX
x48 FADC
Data stream
CPU
SVD
FADC
Zero supp.
Formatter
Repeater
to HLT
~2m
~10m
belle2link TX
x1748
APV25s
Aurora link
TRG/CLK signals
PXD region of interest gen
VME
to PXD
x4 buffer
Data size reduction
FADC Ctrl
APV trig gen
Decoder
Cu cable
Trigger/
timing
distributor
Central TRG
FADC-Ctrl
SVD readout system
Central DAQ
Prototypes of all other remaining components have been developed as well.

14. SVD+PXD DAQ Test @ DESY Beam Line
Event display
w/ magnetic field
Test SVD modules
Reconstructed
track
4-layers test SVD modules
Jan.-Feb. 2014
APV25 chips
in light-shielding box
e⁻ beam (2-6 GeV)
DSSD sensor
Test SVD modules
Superconducting solenoid magnet (max. 1T)
(max. 1T)

15. SVD+PXD DAQ Test @ DESY Beam Line
Cluster charge distribution
Cluster size distribution
The peak corresponds to ~22000 e⁻.
Cluster hit efficiency for tracks
From the resulting high efficiency, we confirm our common mode correction and zero-suppression keep SVD hits with high efficiency.
Efficiency
efficiency: 99.4%
Position of track projection [cm]

16. SVD TEST @ CERN BEAM FWD/BWD module, no cooling
L5 module, with cooling

17. Global Schedule High level milestones
First mass production ladder (L4-L6)
Oct. 2015
2nd beam test
Jan.-Feb. 2016
Start of ladder mount to support structure
Apr. 2016
SVD readiness in KEK
Feb. 2017
PXD readiness in KEK
Apr. 2017
PXD+SVD integration
Jun. 2017
PXD+SVD combined cosmic ray test
PXD+SVD installation
Apr. 2018
Start of physics run
4Q 2018

18. Summary
Precision B-decay vertex detection is a crucial issue to access to physics beyond the SM.
Highly hermetic vertex detectors had been designed.
DAQ system design is confirmed working in the beam test.
The first electrically full functioning ladder completed in the April demonstrates well established ladder assembly procedure.
Ladder mass production is forthcoming.
Belle II physics run will start in 4Q 2018.