VLSI Design Methodologies EE116B (Winter 2001): Lecture # 4

Reading for this Lecture Chapter 11 of Rabaey’s book

Four Phases in Creating a Chip This Lecture Future Lecture Previous Lecture

The Design Problem Source: sematech97 A growing gap between design complexity and design productivity [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Profound Impact on the way VLSI is Designed The old way: manual transistor twiddling expert “layout designers” entire chip hand-crafted okay for small chips… but cannot design billion transistor chips in this fashion The new way: using CAD tools at high level tools do the grunge work… high levels of abstractions synthesis from a description of the behavior libraries of reusable cores, modules, and cells Chip design increasingly like object-oriented software design! [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Designing a VLSI Economic viability affected by design time Design time affected by the efficiency of concept  requirements  architecture  logic/memory  circuit  layout Continuous trade-off between performance (speed, area, power) size of die (hence cost of die and packaging) time of design (hence cost of engineering & schedule) ease of test generation and testability

VLSI-design Tools & Methodologies Goal is to reduce complexity, increase productivity, and increase chances of a working chip Key is the use of Constraints and Abstractions Constraints help automate the procedure by simplifying the problem Abstractions collapse detail and arrive at a simpler problem to deal with Different design methodologies different types of constraints and trade-offs choice driven by economics!

Design Domains Behavioral Structural Physical (geometrical) what a system does Structural how entities are connected together to perform the behavior Physical (geometrical) how to build a structure that has the required connectivity to implement the prescribed behavior

Levels of Design Abstractions for Each Design Domain Architectural Algorithmic Module or functional block Logical Switch Circuit Device etc.

Design Abstraction Levels [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Design Methodology Design process traverses iteratively between behavior, structure, and geometry abstractions CAD tools providing more and more automation

A More Simplified Flow

Principles of Structured Design Techniques Hierarchy Regularity Modularity Locality

Hierarchy Divide and conquer Analogy with software compose system from simpler widgets Analogy with software break large programs into threads and subroutines Hierarchy can be there in all domains behavior, structural, physical The hierarchy in different domains may not correspond e.g. a structural hierarchy may not map well to physical

Example of Structural Hierarchy

Example of Physical Hierarchy

Example of Structural Hierarchy

Example of Physical Hierarchy

Repartitioning Structural Hierarchy to Fit Physical Hierarchy

Regularity Hierarchy breaks a system into submodules but this may not solve the complexity problem there may not be any regularity in the subdivision we just end up with a large # of different submodules Regularity as a guide subdivide into a set of similar building blocks e.g. RAM composed of identical cells Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible

Regularity (contd.) Regularity can be at all levels circuit: use identically sized transistors gate: similar gate structures higher level: architectures with identical processors Regularity helps in many ways correct by construction reuse of design simplify verification of correctness

Circuit-level Regularity Example A 2-1 Mux D-type edge triggered flipflop One-bit full add All designed using inverter and tristate buffer

Modularity Condition that submodules have “well-defined” functions and interfaces in addition to regularity and hierarchy ‘Well-formed” modules allow their interaction with others to be “well-characterized” Depends on the situation e.g. in s/w a subroutine has a well-defined interface argument list with typed variables e.g. in IC a well-defined physical, structural, and behavioral interface pin position, layer, size, signal type, electrical characteristics, logic function

Why Modularity? Allows the design of system to be broken up with confidence that the system will work as specified when the parts are combined Allows team design by a number of designers Examples: bad use: use of transmission gates as inputs internal signals now depend on source impedance bad use: use dynamic CMOS logic but fail to latch or register the inputs timing of each module will have to be checked

Example of Poor Modularity

Locality Modularity provided “well-characterized” interfaces internals of modules unimportant to exterior interface internal details remain at the local level a form of “information hiding” reduces apparent complexity of the module Locality ensures that connections are between neighboring modules, avoiding long-distance connections Example: timing locality so that time critical operations are local clock generation and distribution network entire clock cycle for global signals to traverse chip placement so that global wiring is minimized Analogy with software global variables are to be avoided

Parallels between H/W & S/W Design Strong parallels in the way VLSIs are designed and the way complex software is HDLs used to describe hardware systems in essence merge these two disciplines software methods used to define hardware Hardware-software Co-design But, can’t ignore hardware aspects entirely important since a physical chip is the end product

Typical VLSI Design Flow

Types of Tools Analysis and verification Implementation and synthesis Testability techniques

Design Analysis and Verification Accounts for largest fraction of design time More efficient when done at higher levels of abstraction select of correct analysis level can reduce verification time by orders of magnitude Two approaches: simulation: depends on choice of excitation verification: extracts desired results directly from circuit description [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Simulation Approaches Key distinction is how are data & time represented? Circuit-level simulation (e.g. Spice) Switch-level simulation (e.g. IRSIM) transistors as switches with resistance Gate-level (logic) simulation now obsolete due to logic synthesis Functional simulation (e.g. VHDL, Verilog) primitives of arbitrary complexity Behavioral simulation (e.g. VHDL) only mimic I/O functionality hardware delay loses its meaning

Digital Data as Analog Signals Circuit Simulation Both Time and Data treated as Analog Quantities Also complicated by presence of non-linear elements (relaxed in timing simulation). Impractical for large circuits [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Representing Data as Discrete Entity Discretizing the data using switching threshold {0,1,X} representation of data The linear switch model of the inverter [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Discretizing Time Evaluate circuits only at “interesting” times Event-driven simulation evaluate gates only at a future time of interest current time + gate delay for more accuracy gate delay = function of load still, events can happen at any time Further simplification: unit-delay model events only at multiples of a unit time Even further simplification: zero-delay model events at clock a.k.a. clock or cycle based simulation

Circuit vs. Switch Level Simulation [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Structural Description of Accumulator Design defined as composition of register and full-adder cells (“netlist”) Data represented as {0,1,Z} Time discretized and progresses with unit steps Description language: VHDL Other options: schematics, Verilog [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Behavioral Description of Accumulator Design described as set of input-output relations, regardless of chosen implementation Data described at higher abstraction level (“integer”) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Behavioral Simulation of Accumulator Discrete time Integer data (Synopsys Waves display tool) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Timing Verification Enumerates and rank orders critical timing paths Critical path Enumerates and rank orders critical timing paths No simulation needed! (Synopsys-Epic Pathmill) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Issues in Timing Verification False Timing Paths [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Design Verification Simulation only tells how circuit reacted to input excitation that was specified Verification tools analyze design and find problems Example: electrical verification transistor sizing for rise/fall time constraints timing verification find critical path functional (formal) verification compare circuit behavior against designer’s specification proof that the two are “equivalent”, i.e. proof that the circuit will work e.g. prove that two state machines are equivalent

Implementation Methodologies [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Economics of Implementation Decision depends on Non-recurring engineering cost engineering design cost (personnel, support etc.) prototype manufacturing cost Production cost (Recurring cost) wafer cost, processing cost die per wafer die yield per wafer, packaging yield, final test yield Fixed costs data sheets, cost of sales Important to estimate design time and design cost guide to select the design method

Choosing a Design Style

Custom Circuit Design When performance & design density important High cost and long time-to-market justified only if high volumes design will be reused (e.g. library cell) cost no concern due to CAD tools, custom design is minimal

Tools for Custom Design Layout editor (e.g. Virtuoso) Symbolic layout relative positioning followed by compactor Design rule checking technology file, hierarchical DRC Circuit extraction schematic from layout transistors, caps, resistances, inductances Netlist comparison and netlist isomorphism Back annotation from layout to schematic

Custom Design - Layout Editor Magic Layout Editor (UC Berkeley) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Symbolic Layout Dimensionless layout entities Only topology is important Final layout generated by “compaction” program Stick diagram of inverter [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Cell-based Design Methodology Why? Shorter design time! but, larger penalty Array-based design (later) cuts process steps and reduces time even further… Standard cell library of logic gate (nand, and, or etc.) design as a schematic or netlist of cells from library layout is generated automatically in rows design and composition of library is the main issue what fanout to design for? Alternative versions of cells with different drive

Standard Cell Libraries Typically contain a few hundred cells inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops Each gate type can have multiple implementations to provide adequate driving capability for different fanouts e.g the inverter gate can have standard size transistors, double size transistors, and quadruple size transistors the chip designer can choose the proper size to achieve high circuit speed and layout density Cells characterized for various metrics, such as delay time vs. load capacitance Circuit, timing, and fault simulation models cell data for place-and-route mask data Cells designed such that they can be abutted to form rows

Standard Cell Based Design Routing channel requirements are reduced by presence of more interconnect layers [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Standard Cell - Example [Brodersen92] [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Standard Cell - Example 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Automatic Cell Generation (Compiled Cells) Random-logic layout generated by CLEO cell compiler (Digital) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Module Generators Logic gate okay for random logic But, inefficient for regular structures e.g. carry chain capacitance in N-bit adder Standard cells do not exploit regularity Structured custom design macrocell generators, e.g. memories, multipliers interconnects by abutment in both dimensions datapath compilers abutment in one dimension, routing in the other usually “parameterizable”

Datapath Compilers: Linear Placement [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Datapath Layout

Macrocell Design Methodology Floorplan: Defines overall topology of design, relative placement of modules, and global routes of busses, supplies, and clocks Interconnect Bus Routing Channel [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Channel Routing

Macrocell-based Design Example SRAM SRAM Data paths Routing Channel Standard cells Video-encoder chip [Brodersen92] [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Array-based Design Cuts process steps and reduces time even further… Several types: Mask programmable arrays pre-diffused so that several masks are eliminated typically, only top metalization needs to be done standard packages to keep packaging cost low e.g. gate array, sea of gates Pre-wired arrays avoid detailed manufacturing totally analogy with memory

Processing Steps in Gate Array Implementations

Gate Array - Sea-of-gates Uncommited Cell Committed Cell (4-input NOR) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Sea-of-gate Primitive Cells Using oxide-isolation Using gate-isolation [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Pre-wired Arrays Categories of pre-wired arrays (or, field programmable gate arrays) fuse based (program once) non-volatile EPROM or EEROM based RAM based [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Programmable Logic Devices PAL PLA PROM [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

EPLD Block Diagram Macrocell Primary inputs Courtesy Altera Corp. [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Antifuse Normally high resistance (> 100 M) on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure (200-500)

Antifuse-based Actel FPGAs Standard-cell like floorplan [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Detailed Interconnect Programming interconnect using anti-fuses [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Basic Block in Actel FPGA

RAM-based FPGAs [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Basic Block (CLB) in RAM-based FPGAs Courtesy of Xilinx [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

RAM-based FPGA Xilinx XC4025 [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

General Architecture of Xilinx FPGAs

Switch Matrices & Interconnection between CLBs

XC2000 CLB of the Xilinx FPGA

Overview of VLSI Design Styles

Design synthesis Behavior  Structure

Taxonomy of Synthesis Tasks [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Circuit Synthesis Logic equations  transistor schematics selection of circuit style complementary static, pass-transistor, dynamic etc. construction of logic network e.g. Euler path techniques Transistor sizing to meet performance constraints major impact on area, power, timing subtle process… sensitive to parasitics usually circuit modeled by equivalent RC circuit detailed knowledge of subsequent layout process needed for estimation of parasitic capacitances

RTL or Logic Synthesis Generate structural view of a logic level network Many ways of specifying: FSMs, schematics, boolean equations, HDL etc. Two step process: technology independent phase logic optimized using boolean & algebraic manipulation technology mapping phase

Evolution of RTL Synthesis 2-Level logic minimization Espresso from Berkeley Suited for PLAs & PALs which were used a lot in 80s Sequential and state-machine synthesis state minimization, state encoding Multilevel logic synthesis Mis-II from Berkeley standard-cell and FPGA Full blown RTL synthesis from HDL e.g. Synopsys’s VHDL compiler, Berkeley’s SIS

Example: Multi-level Logic Synthesis Adder: S = (A  B)  Ci Co = A.B + A.Ci + B.Ci

Architecture Synthesis Also called behavior or high-level synthesis Generate architecture from task description under constraints on area, speed, power etc. Three phases allocation: figures out busses, execution units etc. assignment: binds behavior operations to hardware resources scheduling: order of operations Also, transformations that manipulate input behavior to obtain superior solution pipelining, parallelization etc.

Example of Architecture Synthesis ;

Alternative Solution

Design-Evaluation Space

Design-Evaluation Space for a Logic Function

Area, Latency, Cycle-time Design Evaluation Space

Another Example of Architecture Synthesis

Alternative Implementations