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Chapter 3 Logic Gates
Inverter Truth Table
Inverter Timing DiagramFigure Inverter operation with a pulse input. Figure The inverter complements an input variable.
Inverter Timing Diagram
Figure 3--9 All possible logic levels for a 2-input AND gate.AND Gate Operation Figure All possible logic levels for a 2-input AND gate.
AND Gate Truth Table Figure Boolean expressions for AND gates with two, three, and four inputs.
AND Gate Truth Table
AND Gate Timing DiagramFigure Example of pulsed AND gate operation with a timing diagram showing input and output relationships.
AND Gate Timing DiagramAll must be high for the output to be high
AND Gate Application ExampleFigure An AND gate performing an enable/inhibit function for a frequency counter.
Figure 3--18 All possible logic levels for a 2-input OR gateOR Gate Operation Figure All possible logic levels for a 2-input OR gate
OR Gate Truth Table Figure Boolean expressions for OR gates with two, three, and four inputs.
OR Gate Timing Diagram Figure Example of pulsed OR gate operation with a timing diagram showing input and output time relationships.
OR Gate Timing Diagram All must be low for the output to be low
OR Gate Application ExampleFigure A simplified intrusion detection system using an OR gate.
Figure 3--26 Operation of a 2-input NAND gate.NAND Gate Operation Figure Operation of a 2-input NAND gate.
NAND Gate Truth Table
NAND Gate Timing Diagram
Figure 3--29 Standard symbols representing the two equivalent operations of a NAND gate.
Figure 3--34 Operation of a 2-input NOR gate.NOR Gate Operation Figure Operation of a 2-input NOR gate.
NOR Gate Truth Table
NOR Gate Timing Diagram
Figure 3--37 Standard symbols representing the two equivalent operations of a NOR gate.
Figure 3--42 All possible logic levels for an exclusive-OR gateXOR Gate Operation Figure All possible logic levels for an exclusive-OR gate
XOR Gate Truth Table
XOR Gate Application ExampleFigure An XOR gate used to add two bits.
Figure 3--45 All possible logic levels for an exclusive-NOR gate.XNOR Gate Operation Figure All possible logic levels for an exclusive-NOR gate.
XNOR Gate Truth Table
Fixed-Function Logic : IC GatesCMOS (Complementary Metal-Oxide Semiconductor) TTL (Transistor-Transistor Logic) CMOS – lower power dissipation
Figure Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin numbers and basic dimensions.
Figure 3--50 Pin configuration diagrams for some common fixed-function IC gate configurations.
Figure Logic symbols for hex inverter (04 suffix) and quad 2-input NAND (00 suffix). The symbol applies to the same device in any CMOS or TTL series.
Performance Characteristics and ParametersPropagation delay Time DC Supply Voltage (VCC) Power Dissipation Input and Output Logic Levels Speed-Power product Fan-Out and Loading
Figure 3--52 Propagation Delay
Higher fan-out = gate can be connected to more gate inputs.Figure The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate inputs.
Figure 3--57 The partial data sheet for a 74LS00.
Figure 3--59 The effect of an open input on a NAND gate.Troubleshooting Figure The effect of an open input on a NAND gate.
Figure 3--60 Troubleshooting a NAND gate for an open input with a logic pulser and probe.
Figure 3--65 An example of a basic programmable OR array.Programmable Logic Programmable Arrays Figure An example of a basic programmable OR array.
Figure 3--66 An example of a basic programmable AND array.
Figure 3--67 Block diagram of a PROM (programmable read-only memory).4 Types of SPLDs Figure Block diagram of a PROM (programmable read-only memory).
Figure 3--68 Block diagram of a PLA (programmable logic array).
Figure 3--69 Block diagram of a PAL (programmable array logic).
Figure 3--70 Block diagram of a GAL (generic array logic).
Figure 3--71 Logic Gate Summary
Numbers Treasure Hunt Following each question, click on the answer. If correct, the next page will load with a graphic first – these can be used to check.
1 A B C
Trend for Precision Soil Testing % Zone or Grid Samples Tested compared to Total Samples.
AP STUDY SESSION 2.
Slide 1Fig 26-CO, p.795. Slide 2Fig 26-1, p.796 Slide 3Fig 26-2, p.797.
Slide 1Fig 25-CO, p.762. Slide 2Fig 25-1, p.765 Slide 3Fig 25-2, p.765.
Slide 1Fig 24-CO, p.737. Slide 2Fig 24-1, p.740 Slide 3Fig 24-2, p.741.
Copyright © 2003 Pearson Education, Inc. Slide 1 Computer Systems Organization & Architecture Chapters 8-12 John D. Carpinelli.
Sequential Logic Design
Copyright © 2013 Elsevier Inc. All rights reserved.
Copyright © 2011, Elsevier Inc. All rights reserved. Chapter 6 Author: Julia Richards and R. Scott Hawley.
David Burdett May 11, 2004 Package Binding for WS CDL.
Local Customization Chapter 2. Local Customization 2-2 Objectives Customization Considerations Types of Data Elements Location for Locally Defined Data.
Create an Application Title 1Y - Youth Chapter 5.
Custom Services and Training Provider Details Chapter 4.
Add Governors Discretionary (1G) Grants Chapter 6.
1 10 pt 15 pt 20 pt 25 pt 5 pt 10 pt 15 pt 20 pt 25 pt 5 pt 10 pt 15 pt 20 pt 25 pt 5 pt 10 pt 15 pt 20 pt 25 pt 5 pt 10 pt 15 pt 20 pt 25 pt 5 pt BlendsDigraphsShort.
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