Interconnection in IC Assembly Chapter 4 Part 2 Tape Automated Bonding (TAB), Flip Chip

Tape Automated Bonding (TAB) Tape Automated Bonding (TAB), is the process of mounting a die on a flexible tape made of polymer material, such as polyimide. It is based on the fully automated bonding of one end of the copper beam lead to an IC and the other end of the lead to a conventional package or PWB. Tape automated bonding (TAB) also known as “gang” bonding technique in which bonds (on the chip or lead frame or substrate) are formed simultaneously.

Tape Automated Bonding (TAB) There are several TAB tape structures – planar tape, bumped tape, transfer-bumped tape, and ball tape.

Advantages of Tape Automated Bonding (TAB) Ability to handle small bond pads and finer pitches on the IC. Elimination of larger wire loops. Low profile interconnection structures for thin packages. Improved conduction heat transfer for thermal management. Improved electrical performance. Ability to handle high I/O counts. Ability to burn in on tape before device commitment. Reduce weight.

Disadvantages of Tape Automated Bonding (TAB) Basically a peripheral interconnection technique with no active circuitry under the chip bond pads. Package size tends to increase with larger I/O counts. Process inflexibility due to hard tooling requirements of the flex circuits, bond head and etc. Additional wafer processing steps required for bumping Larger capital equipment investment required. Difficulty in assembly rework. Specialty materials and equipment requirements.

Tape Automated Bonding (TAB)

Tape Automated Bonding (TAB)

Tape Automated Bonding (TAB)

TAB - IC Bond Pad Interface Inner Lead Bonding

TAB - IC Bond Pad Interface

Tape Automated Bonding (TAB) Electrical performance – Improved electrical performance, due to short circuit lead lengths between the chip and substrate reducing impedance and signal delays. Production examples – Tape Ball Grid Array (TBGA), TapePak@ (based on Quad Flat Pack), Pentium TCP.

Flip Chip First invented in 1962 at IBM; called Solid Logic Technology Converted in 1970 to Controlled Collapse Chip Connection (C4) C4 is one type of mounting used for semiconductor devices, such as Chips, MEMS or components, which is using solder bumps instead of wire bonds. The solder bumps are deposited on the chip pads, located on the top side of the wafer, during the final wafer processing step. In order to mount the chip to external circuitry (on a circuit board or another wafer or a chip), it is flipped around – the top-side facing down the mounting area. The solder bumps are used to connect directly to the associated external circuitry.

Flip Chip Basic structure of flip chip consists of IC or chip, interconnection system and substrate. IC or chip –Si, GaAs, IP, Si-Ge and etc Interconnection system (IC bond pad interface) –under bump metallization (UBM), chip bumps, bond material between the bump and substrate metallization, encapsulation and substrate metallization Substrate –Ceramic (C4), epoxy glass laminate, polymer thin-film build-up, resin coated copper (RCC), glass, silicon, dieletric-coated metal, liquid crystal polymer, dielectric metal matrix composite, low-temperature co-fired ceramic (LTCC), ceramic thick film, multilayer high temperature co-fired ceramic and etc.

Flip Chip

Flip Chip

Flip Chip

Flip Chip

Flip Chip Technology

Note the five components of the joints Flip Chip Interconnect System Note the five components of the joints - Underbump metallization– Chip bumps – Bond materials between bump and substrate metallization – Substrate metallization – Encapsulant and substrate metallization

Concept of the Flip Chip Interconnect System

Advantages of Flip Chip Lower cost than wirebonding since the bumping done at wafer level; high I/O; all connections are made simultanenously. Higher reliability than either wirebonding or beam lead bonding (TAB). Book claims flip chip was succesfully made from 1960-1990 without any failure related to FC  implemented for ceramic substrates Better electrical performance due to lower resistance, capacitance and inductance. Provide shorthest path between IC and substrate. Repairability—If an IC was defective, either during assembly or during usage, it can be removed and a new IC if flip chip bonded on the same ceramic again. Improved chip designs may be substituted on multichip modules

Disadvantages of Flip Chip More cost on infrastructures. Involved of a few process before interconnection can be made. Unprotected flip chips are prone to thermally induced cracking solder connections and even damage the device itself. The effects of this thermal mismatch can be lessened considerably with the use of an underfill. Not a good choice (low cost solution) for less I/O

Flip Chip - Process steps

Flip Chip - Process steps Integrated circuits are created on the wafer Pads are metalized on the surface of the chips Solder dots are deposed on each of the pads Chips are cut Chips are flipped and positioned so that the solder balls are facing the connectors on the external circuitry Solder balls are then remelted (typically using ultrasound) Mounted chip is “underfilled” using an electrically-insulating adhesive

Common Wirebonding related Failure Mechanisms

Common Wirebonding related Failure Mechanisms Ball Bond Neck Break - breakage of the wire at the neck of the Au ball bond. Common Causes: incorrect wirebond parameter settings, incorrect wire looping, die-to-package delamination, excessive wiresweeping during mold, excessive die overcoat, 'bamboo' grain structure due to excessive thermal treatment Midspan Wire Break - breakage along the span of the wire. Common Causes: wire nicks or damage, wire corrosion, tight wire looping, excessive wiresweeping, electrical overstress Bond-to-Metal Shorting - electrical shorting between the bond and a metal line on the die. Common Causes: incorrect wirebond parameter settings, incorrect bond placement, insufficient bond pad-to-metal distance

Under Bump Metallization (UBM) UBM is a multilayer thin films between IC metallization, passivation layer and solder bump. The structure consists of an adhesion layer covering up the chip metallization (Cr, Ti, Ni, W TiW ) A barrier layer (Cr, W, Ti, TiW, Ni, Cr-Cu) A wetting layer (Cu, Ni, Pd, Pt) An anti-oxidation barrier layer (Au)

Under Bump Metallization (UBM)

Under Bump Metallization (UBM) UBM is necessary. To protect the Al metallized chip from moisture and corrosion. To remove the Al2O3 and provide a good adhesion to Al and reduce the interfacial resistance. Barrier layer to prevents the solder (mainly Sn) from corroding the Al or dewetting Cr wetting layer. Barrier layer is to prevent diffusion of metal species and ionic contaminants into the chip and adhesion layer. Such diffusion can results in formation of brittle intermetallic compounds. Wetting layer because solder will not wet the metal deposited for the barrier or bare Al.

UBM Deposition Technique Electroplated Evaporation Sputtering Electroless

UBM Deposition Technique (Evaporation)

UBM Deposition Technique (Evaporation) Evaporation deposition technology start with cleaning process is performed to remove oxides or photoresist prior to metal deposition. The cleaning also serves to roughen the wafer passivation and surface of the bond pad in order to promote better adhesion of the UBM. Then, the chromium, chrominum/copper, copper and Au layer are deposited through sequential evaporation process to form a multilayer thin film UBM. After that a high lead solder is then evaporated on top of the UBM to form a thick deposit of 97Pb/Sn or 95Pb/Sn. Lastly, the solder is reflow to form a sphere solder ball. During the UBM and solder bump deposition, the metal mask is used for patterning.

UBM Deposition Technique (Electroless)

UBM Deposition Technique (Electroless) In electroless nickel bumping, the process starts with the wafer back side coating to prevent from nickel plated on the exposed silicon. The following next is cleaning process, used to remove contaminant on the passivation and Al bond pad. A second cleaning process is then applied to removes thick Al oxides and prepares the surface for metal deposition. After that is the zincation process. It activates the Al bond pads surface for Ni deposition. A thin zinc layer is deposited on Al which is substitutes by Ni in the Ni bath. Finally, a thin gold layer is deposited on the Ni from an immersion gold bath to prevent the oxidation of Ni before soldering and also help to improve solderability with solder ball.

Electro-Plated Solder Bumps

Electroless UBM

Flip Chip Bumps The bumps provide four functions Electrical connection between the chip and the substrate A heat dissipation path from the chip Environmental protection to the final metal layer (Al bond pad) A structural link between the chip and substrate

Various Flip Chip Bumps Stacked Stud Bumps Gold Stud Bumps Indium Bumps Solder Bumps Nickel Bumps Gold Bumps

Solder Bumps Solder bumps are deposited onto the UBM – Several method: Evaporation Electroplated Screen printing Solder jet technology Ball drop Micro Ball Placement and etc.

Solder Bumps - Printing

Solder Jet Technology

Solder Ball Bumping (SBB) – Ball Drop

Micro Ball Placement

Solder Bumps Solder primary material system High temperature with melting points in excess of 250°C (examples include 95%Pb - 5%Sn and 97% Pb – 3%Sn) Moderate temperature with melting points between 200 and 250°C (examples include 95.5%Sn-3.5%Ag-1%Cu; CASTIN® Cu-Ag-Sb-Sn and 85.9%Sn-3.1%Ag-10%In-1%Cu and 96.5% Sn-3.5% Ag) Low temperature with melting points less than 200°C (examples include 37%Pb-63%Sn eutectic, 88% In – 12%Pb, 100% In and 48% Sn-52% In)

Flip Chip (Bump Interconnection) Processing There are several interconnection processing technologies: Solder interconnect processing Isotropic conductive adhesive Anisotropic conductive adhesive

Solder interconnect processing

Conductive Adhesive Interconnection System The basic structures of two major adhesive interconnection systems: Isotropic conductive adhesive Anisotropic conductive adhesive

Conductive Adhesive Interconnection System

Solder Bumped Flip Chip on Organic Substrate Stencil Printing Solder Paste on PCB Pick & Place part on PCB Room Temperature (25oC) Underfill melting & reflowing (75oC) Forming solder joint (183oC) Organic Substrate Underfill Solder-Bumped Flip Chip Solder Joints TCE of Organic Substrate = 18x10-6/oC TCE of Silicon Chip = 2.5x10-6/oC

Underfill Encapsulation and Processing

Comparison Between Wirebonding and Flip Chip Cost, equipment and infrastructure Overall product cost is high (low throughput) Low cost in equipment setup Low cost in infrastructure and floor space Overall product cost is low (high throughput) High cost in equipment setup High cost in infrastructure and floor space Process cycle time Slower interconnection rates (low I/O) due point-to-point processing of each wirebond Fast interconnection rates (high I/O) due to all connection are made simultaneously Chip interconnection count Low I/O, connection are only in peripheral i.e. bonds are limited to the periphery of the chip High I/O, it can involve area array connection Electrical Performance Low electrical performance due to long interconnection between die to lead on the leadframe. This will increase impedance, capacitance and inductance thus increase delay in output signal Better electrical performance due to lower resistance, capacitance and inductance. Provide shorthest path between IC and substrate.

Flip Chip on Organic Circuit Board Application Flip Chip – Product Examples Flip Chip on Organic Circuit Board Application

Flip Chip for a Consumer Product Flip Chip – Product Examples Flip Chip for a Consumer Product

Flip Chip – Product Examples