1. Multilayer thin film technology for the STS electronic high density interconnection
E. Atkin
Moscow Engineering Physics Institute (State University) – MEPhI,
M. Merkin, A.Voronin
Skobeltsyn Institute of Nuclear Physics / Moscow State University – SINP / MSU,
Kazak
Avangard
CBM Collaboration meeting
March 9-12, 2005

2. The Interconnection gap
By Eric Beyne
IMEC
Requires new high density Interconnect technologies
PCB scaling
Advanced PCB
Size scaling
Thin film lithography based
Interconnect technology
IC scaling
Reduced Gap
Time

3. WHY ? 25 um pitch space flexibility reliability of the contact
Material budget
25 um pitch
space flexibility
reliability of the contact
stress reliability
special bonding
equipment
Difficult to repair
By Eric Beyne

4. Bonding technology IC SPCB Wire bonding FPCB Bond pitch : High density
100 25mm
High density
substrate
SPCB
FPCB
Wire bonding
contact pitch :
800100 mm
Down to 25mm pitch

5. BONDING THIN FILM Technology
By Avangard company

6. High Density Thin Film Interconnects for Digital Applications
By Eric Beyne
IMEC, Kapeldreef 75, B-3001 Leuven
Technology :
Substrates : 150 mm Ø, Si, glass, ceramic, high Tg laminate or metal.
Cu lines, 3-5m thick, down to 10m wide lines & spaces
Metal finish top surface : Cu/Ni/Au
Power & ground layers : 2 m thick Al
Integrated decoupling
capacitors (0.75 nF/mm2)
Automated design
methodology

7. High Density Thin Film Interconnects By Eric Beyne IMEC, Kapeldreef 75, B-3001 Leuven
Solder balls <100 um
60 um flip chip bump pitch
BCB -benzo-cyclobutene

8. Flexible PC board&soldering by Avangard company
polyimide
precise soldering up to 20um pitch to
create high reliability contacts
between the detector and chip
low profile
price is 1Euro**/front-end channel
passive SMD components close the chip
possibility to create capacitors and
inductances by polyimide-metal film
micro connectors 600um high and
300um pitch – easy to repair
SIS ( system in the package)
high frequency interconnection

9. Multilayer thin film technology RrontEnd module RND
FrontEnd chip
Polyimide board (options)
Micro connector
Substrate (?)
Silicon detector

10. PLANS 128 channel front-end chip VA-1will be used for RND
3 technology options:
1. Al chip pad metallization for bonding
2. CU chip pad metallization, two layer polyimide board
for soldering
3. Thin film pad contact with solid substrate, polyimide
lacquer as an insulator between layers.
Options 2 and 3 allow to protect the chip against chemical shock.
Option 3 feature is the same process for metallization of
polyimide board holes and the chip interconnection

11. Option 2 6 5 7 10 – Soldering 4 3 First layer Second layer8 9 9 5 8 7 7
10 – Soldering 7 7 4 3 1 2
First layer
Second layer
Second conductor layer
Soldering pads
Internal Metallized hole
Second layer soldering hole
Soldered contact
Chip
Additional protection
First Insulate layer
First conductor layer
Second Insulate layer

12. Option 2 Steps Cu pad film on the chip Polyimide board production
Chip mounting
? Substrate production, polyimide board with the chip mounting onto substrate
Testing with micro connector

13. Option 3 First conductor layer Substrate Polyimide Chip7 6 5 4 1 8 2 3
First conductor layer
Polyimide
Second conductor layer
Evaporated contact
Substrate
Chip
Glue
Polyimide lacquer

14. Summary Thin film technology interconnection RND started
First result expected this year
Expected price is 1Euro/channel
We really need to test interconnection technologies