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IC packaging and Input - output signals

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Presentation on theme: "IC packaging and Input - output signals"— Presentation transcript:

1 IC packaging and Input - output signals
J. Christiansen, CERN - EP/MIC

2 Requirements to package
Protect circuit from external environment Protect circuit during production of PCB Mechanical interface to PCB Interface for production testing Good signal transfer between chip and PCB Good power supply to IC Cooling Small Cheap December 2003 J.Christiansen/CERN

3 Materials Ceramic Metal (has been used internally in IBM) Plastic
Good heat conductivity Hermetic Expensive ( often more expensive than chip itself !) Metal (has been used internally in IBM) Electrical conductive (must be mixed with other material) Plastic Cheap Poor heat conductivity Can be improved by incorporating metallic heat plate. December 2003 J.Christiansen/CERN

4 Cooling Package must transport heat from IC to environment
Heat removed from package by: Air: Natural air flow, Forced air flow improved by mounting heat sink PCB: Transported to PCB by package pins Liquid: Used in large mainframe computers Resistive equivalent Heat sink IC dice Package I = heat power V= temperature R = K/watt PCB December 2003 J.Christiansen/CERN

5 Package types: Below 1 watt: Plastic Below 5 watt: Standard ceramic
Up to 30 watt: Special 60 layers MCM substrate Active heat sink Water cooled mainframe computer Passive heat sink December 2003 J.Christiansen/CERN

6 Power density is getting problematic
December 2003 J.Christiansen/CERN

7 Chip mounting Pin through hole Surface Mount Devices (SMD)
Pins traversing PCB Easy manual mounting Problem passing signals between pins on PCB (All layers) Limited density Surface Mount Devices (SMD) Small footprint on surface of PCB Special machines required for mounting No blocking of wires on lower PCB layers High density December 2003 J.Christiansen/CERN

8 Traditional packages DIL (Dual In Line) PGA (Pin Grid Array)
Low pin count Large PGA (Pin Grid Array) High pin count (up to 400) Previously used for most CPU’s PLCC (Plastic leaded chip carrier Limited pin count (max 84) Cheap SMD QFP (Quarter Flat pack) High pin count (up to 300) small Package inductance: nH December 2003 J.Christiansen/CERN

9 New package types BGA (Ball Grid Array)
Small solder balls to connect to board small High pin count Cheap Low inductance Package inductance: 1 - 5 nH December 2003 J.Christiansen/CERN

10 CSP (Chip scale Packaging)
Similar to BGA but smaller and thinner Very small packages December 2003 J.Christiansen/CERN

11 MCP (Multi Chip Package)
Mixing of several technologies in same component Yield improvement by making two chips instead of one P6: processor + second level cache December 2003 J.Christiansen/CERN

12 Chip to package connection
Wire bonding Only periphery of chip available for IO connections Mechanical bonding of one pin at a time (sequential) Cooling from back of chip High inductance (~1nH) Flip-chip Whole chip area available for IO connections Automatic alignment One step process (parallel) Cooling via balls (front) and back if required Thermal matching between chip and substrate required Low inductance (~0.1nH) December 2003 J.Christiansen/CERN

13 Multiple Chip Module (MCM)
Increase integration level of system (smaller size) Decrease loading of external signals > higher performance No packaging of individual chips Problems with known good die: Single chip faults: 5% MCM yield with 10 chips: (0.95)10 = 60% Problems with cooling Still expensive December 2003 J.Christiansen/CERN

14 Intel's new Itanium processor
Processor and external components ( L2 cache) Heat pipe for cooling (liquid evaporation in enclosed volume) December 2003 J.Christiansen/CERN

15 Heat pipes Cooling via evaporation of liquid in sealed “pipe”
December 2003 J.Christiansen/CERN

16 Reducing package thickness
December 2003 J.Christiansen/CERN

17 Multiple chips in chip scale packages
Chip staking using bump bonding and wire bonding Folding flexible substrate With multiple bump bonded chips December 2003 J.Christiansen/CERN

18 Exotic packaging 3D stacking Thinned and flexible chips
52 chips stacked December 2003 J.Christiansen/CERN

19 Signal Interface Transfer of IC signals to PCB Package inductance.
PCB wire capacitance. L - C resonator circuit generating oscillations. Transmission line effects may generate reflections Cross-talk via mutual inductance L-C Oscillation PCB trace f =1/(2p(LC)1/2) L = 10 nH C = 10 pF f = ~500MHz Chip L Z C R Transmission line reflections Package December 2003 J.Christiansen/CERN

20 IO signals Direct voltage mode Slew rated controlled
Simple driver (Large CMOS inverter) TTL, CMOS, LV-TTL, etc. Problems when Vdd of IC’s change. Large current peaks during transitions resulting in large oscillations Slew rated controlled Limiting output current during transitions Reduced oscillations (Reduced speed) Imax C Imax Slew rate controlled December 2003 J.Christiansen/CERN

21 HSTL: High speed transceiver logic
Separate power supply (vddq) defining drive levels (1.5v) Intended to drive terminated transmission lines (different classes depending on required current drive) Receiver compares to voltage reference defined as vddq/2. Used for high speed memory interfaces Can also be used differential Current mode Switch current instead of voltage Reduced current surge in power supply of driver Reduced oscillations External resistor to translate into voltage or Low impedance measuring current directly Very good to drive transmission lines (similar to ECL) Driver Receiver vddq Z R vddt I Z R December 2003 J.Christiansen/CERN

22 Differential Switch two opposite signals: signal and signal inverted
Good for twisted pairs Common mode of signal can be rejected Two pins per signal required High speed Twisted pair Differential receiver Only sensitive to differential amplitude (common mode rejection) Differential amplitude Common mode December 2003 J.Christiansen/CERN

23 LVDS (Low Voltage swing Differential signaling)
High speed (up to 250 MHz or higher) Low voltage (independent of Vdd of different technologies) Differential Current mode Constant current in driver power supply (low noise) I = > 2.5mA Amplitude > 250 mV (500mv differential) R= ~100ohm Common mode = 1.25v December 2003 J.Christiansen/CERN

24 Power supply Power supply current to synchronous circuits strongly correlated to clock Large current surges when normal CMOS output drivers change state Inductance in power supply lines in package. 10% - 50% of IC pins dedicated to power to insure on-chip power with low voltage drop and acceptable noise. Decoupling capacitors is special purpose packages Modern High end microprocessors needs tens of amperes at a voltage of 1 – 2 volt !. Power pins Clock I V Logic Chip capacitance Board capacitance December 2003 J.Christiansen/CERN

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