Day 30: November 13, 2013 Memory Core: Part 2 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 13, 2013 Memory Core: Part 2 Penn ESE370 Fall2013 -- DeHon

Today Multiport SRAM More DRAM Penn ESE370 Fall2013 -- DeHon

Memory Bank Penn ESE370 Fall2013 -- DeHon

Multiport RAM Penn ESE370 Fall2013 -- DeHon

Mulitport Perform multiple operations simultaneously E.g. Processor register file add r1,r2,r3 R3R1+R2 Requires two reads and one write Penn ESE370 Fall2013 -- DeHon

Simple Idea Add access transistors to 5T Penn ESE370 Fall2013 -- DeHon

Watch? What do we need to be careful about? Penn ESE370 Fall2013 -- DeHon

Adding Write Port Penn ESE370 Fall2013 -- DeHon

Write Port What options does this raise? Penn ESE370 Fall2013 -- DeHon

Opportunity Asymmetric cell size Separate sizing constraints Weak drive into write port (Wrestore) Strong drive into read port (Wbuf) Penn ESE370 Fall2013 -- DeHon

Multiple Read Ports What if want more than two read ports? Can we do this again? Penn ESE370 Fall2013 -- DeHon

Multiple Read Ports What should we be concerned about? Penn ESE370 Fall2013 -- DeHon

Robust Read What makes more robust? Sizing impact? Penn ESE370 Fall2013 -- DeHon

Isolate BL form Mem How make this work? Sizing impact? Penn ESE370 Fall2013 -- DeHon

Isolate BL form Mem Larger, but more robust Precharge Essential for large # of read ports Precharge ReadData High Penn ESE370 Fall2013 -- DeHon

Multiple Write Ports How about multiple write ports? Assuming at most one write per word Penn ESE370 Fall2013 -- DeHon

Multiple Write Ports Penn ESE370 Fall2013 -- DeHon

DRAM Penn ESE370 Fall2013 -- DeHon

Some Numbers (memory) Register as stand-alone element (14T)  4Kl2 Static RAM cell (6T)  1Kl2 SRAM Memory (single ported) Dynamic RAM cell (DRAM process)  100l2 Dynamic RAM cell (SRAM process)  300l2 Penn ESE370 Fall2013 -- DeHon

1T 1C DRAM Simplest case – Memory is capacitor Feature of DRAM process is ability to make large capacitor compactly Penn ESE370 Fall2013 -- DeHon

DRAM Capacitors Sunami, Solid State Circuit, January 2008 http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2171&path=sscs/08Winter&file=Sunami.xml Penn ESE370 Fall2013 -- DeHon

DRAM Trench Capacitor Sunami, Solid State Circuit, January 2008 http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2171&path=sscs/08Winter&file=Sunami.xml Penn ESE370 Fall2013 -- DeHon

DRAM Capacitance Scaling Sunami, Solid State Circuit, January 2008 http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2171&path=sscs/08Winter&file=Sunami.xml Penn ESE370 Fall2013 -- DeHon

3T DRAM Penn ESE370 Fall2013 -- DeHon

3T DRAM How does this work? Write? Read? Penn ESE370 Fall2013 -- DeHon

3T DRAM Correct operation not sensitive to sizing Does not deplete cell on read No charge sharing with stored state All NMOS (single well) Precharge ReadData Must use Vdd+VTN on W to write full voltage Penn ESE370 Fall2013 -- DeHon

Energy Penn ESE370 Fall2013 -- DeHon

Single Port Memory What fraction is involved in a read/write? What are most cells doing on a cycle? Reads are slow Cycles long  lots of time to leak Penn ESE370 Fall2013 -- DeHon

ITRS 2009 45nm C0 = 0.045mm × Cg,total High Performance Low Power Isd,leak 100nA/mm 50pA/mm Isd,sat 1200 mA/mm 560mA/mm Cg,total 1fF/mm 0.91fF/mm Vth 285mV 585mV C0 = 0.045mm × Cg,total Penn ESE370 Fall2013 -- DeHon

High Power Process V=1V d=1000 g=0.5 Waccess=Wbuf=2 Full swing for simplicity Csc = 0 (just for simplicity, typically <Cload) BL: Cload=1000C0 ≈ 45 fF = 45×10-15F WN = 2  Ileak = 9×10-9 A P= (45×10-15) freq + 1000×9×10-9 W Penn ESE370 Fall2013 -- DeHon

Relative Power P= (45×10-15) freq + 1000×9×10-9 W Crossover freq<200MHz How partial swing on bit line change? Reduce dynamic energy Increase percentage in leakage energy Reduce crossover frequency Penn ESE370 Fall2013 -- DeHon

Consequence Leakage energy can dominate in large memories Care about low operating (or stand-by) power Use process or transistors with high Vth Reduce leakage at expense of speed Penn ESE370 Fall2013 -- DeHon

Idea Memory can be compact Rich design space Demands careful sizing Penn ESE370 Fall2013 -- DeHon

Admin Project 2 out Friday here for Memory Periphery Monday in Detkin Milestone due Tuesday Friday here for Memory Periphery Monday in Detkin Penn ESE370 Fall2013 -- DeHon