Falcon-E : Introduction Eight GPRs: R0, R1, …, R7; 32-bits each Two 32-bit special purpose registers: BP and SP Two 32-bit system registers transparent to the programmer: PC and IR Memory word size: 32 bits Memory space size: 232 bytes Memory organization: 232 x 8 bits Memory accessed in 32 bit words ( i.e., 4 byte chunks) Little-endian byte storage

Review

CS501 Advanced Computer Architecture Lecture10 Dr.Noor Muhammad Sheikh

Programmer’s view of the Falcon-E 31 R0 R1 R7 Register file IR PC CPU : SP BP 7 7 1 2 : 232-1 Main memory Input/Output

Falcon-E Notation [R3] means contents of register R3 M[8] means contents of memory location 8 A memory word at address 8 is defined as the 32 bits at addresses 11, 10, 9, and 8 (little-endian)

Falcon-E Notation Special notation for 32-bit memory words M[8]<31…0>:=M[11]©M[10]©M[9]©M[8] (© is used to represent concatenation) M[8] M[9] M[10] M[11] 7 8 15 16 23 24 31 MS Byte LS Byte One memory “word” 8 9  Memory addresses 10 11

Falcon-E : instruction formats

Encoding for the GPRs to be used in place of ra, rb, or rc Register Code R0 000 R4 100 R1 001 R5 101 R2 010 R6 110 R3 011 R7 111

Encoding for the SPRs to be used in place of rb in lds and sts instructions Register Code SP 000 BP 001

Type A nop (op-code = 0) useful in pipelining ret (op-code = 15) iret (op-code = 17) near jmp (op-code = 18)

Type B push (op-code = 8) pushes register to stack push R4 pop (op-code = 9) pops data from stack to register pop R7 ld (op-code = 10) ld R7, [1254h] st (op-code = 12) st R7, [1254h]

Type C lds (op-code = 4) load special purpose register lds SP, R1 R[1] SP sts (op-code = 5) store special purpose register sts R3, BP BP R[3] in (op-code = 6) load register from IO device in R5, R4(100) R[5] IO[R[4]+100] out (op-code = 7) store register to IO device out R8, R6(36) IO[R[6]+36] R[8]

If the constant is negative, this becomes a subtract instruction Type C addi (op-code = 2) immediate 2’s complement addition addi R3, R4, 56 R[3] R[4] + 56 andi (op-code = 2) immediate logical AND andi R3, R4, 56 R[3] R[4] & 56 ori (op-code = 2) immediate logical OR ori R3, R4, 56 R[3] R[4] ~ 56 If the constant is negative, this becomes a subtract instruction

register addressing mode Type D add (op-code = 1) 2’s C register addition add R3, R5, R6 R[3] R[5] + R[6] sub (op-code = 1) 2’s C register subtraction sub R3, R5, R6 R[3] R[5] - R[6] and (op-code = 1) logical AND operation between registers and R8, R3, R4 R[8] R[3] & R[4] or (op-code = 1) logical OR operation between registers or R8, R3, R4 R[8] R[3] ~ R[4] register addressing mode

FUNCTIONAL GROUPS OF INSTRUCTIONS Control Instructions Mnemonic Opcode Function Dec Bin No Operation nop 00000 -

FUNCTIONAL GROUPS OF INSTRUCTIONS Arithmetic Instructions Mnemonic Opcode Function Dec Bin Add add 1 00001 0000 Add Immediate addi 2 00010 Subtract sub 0001 Subtract Immediate subi Multiply mul 0010 Multiply Immediate muli Divide div 3 0011 Divide Immediate divi

FUNCTIONAL GROUPS OF INSTRUCTIONS Logic Instructions Mnemonic Opcode Function Dec Bin And and 1 00001 4 0100 And Immediate andi 2 00010 Or or 5 0101 Or Immediate ori Xor xor 6 0110 Xor Immediate xori

FUNCTIONAL GROUPS OF INSTRUCTIONS Shift and Rotate Instructions Mnemonic Opcode Function Dec Bin Shift Left shl 1 00001 8 1000 Shift Left Immediate Count shli 2 00010 Rotate Left rol 9 1001 Rotate Left Immediate Count roli Shift Right shr 10 1010 Shift Right Immediate Count shri Shift Right Arithmetic sra 11 1011 Shift Right Arithmetic Immediate Count srai

FUNCTIONAL GROUPS OF INSTRUCTIONS Data Transfer Instructions Mnemonic Opcode Function Dec Bin Move Immediate to GPR movi 3 00011 - Load Special Purpose Register from GPR lds 4 00100 Store Special Purpose Register to GPR sts 5 00101 Load Register from IO in 6 00110 Store Register to IO out 7 00111 Push GPR to Stack push 8 01000 Pop GPR from Stack pop 9 01001 Load GPR from Memory (Direct Addressing) ld 10 01010 Load GPR from Memory (Displacement Addressing) 11 01011 Store GPR to Memory (Direct Addressing) st 12 01100 Store GPR to Memory (Displacement Addressing) 13 01101

FUNCTIONAL GROUPS OF INSTRUCTIONS Procedure Calls/Interrupts Mnemonic Opcode Function Dec Bin Call call 14 01110 - Return ret 15 01111 Interrupt int 16 10000 Interrupt Return iret 17 10001

FUNCTIONAL GROUPS OF INSTRUCTIONS Branch Instructions Mnemonic Opcode Function Dec Bin Near Jump (Relative) jmp 18 10010 - Far Jump (Direct) 19 10011 Branch If Equal (Relative) bre 20 10100 0000 Branch If Equal (Direct) 21 10101 Branch If Not Equal (Relative) bne 1 0001 Branch If Not Equal (Direct) Branch If Less (Relative) bl 2 0010 Branch If Less (Direct) Branch If Greater (Relative) bg 3 0011 Branch If Greater (Direct)

Instruction Length Fixed versus variable 16 bit versus 32 bit * Code Density is the physical size of the compiled program and it is greater in the case of thirty two bit instructions. * Path Length is the number of instructions executed for a given program and it is smaller for a thirty two bit processor as compared to a sixteen bit processor. * A thirty two bit instruction offers more bits for opcode, larger register file and larger immediate fields thus allowing flexibility and longer jumps.

Instruction Types and Sub-types EAGLE FALCON-A FALCON-E SRC Types 4 Sub-types - 2 3 * Sub-types are the modified forms of some instruction formats in which one or more fields are interpreted differently and sometimes have a special meaning.

Maximum Number of Operands EAGLE FALCON-A FALCON-E SRC 2 3

Number and Size of GPR EAGLE FALCON-A FALCON-E SRC 8 registers, 16 bit wide 32 bit wide 32 registers

Memory Specs. 216 232 216 x 8 232 x 8 16 bit 32 bit 16 bits 32 bits EAGLE FALCON-A FALCON-E SRC Memory Space 216 232 Organization 216 x 8 232 x 8 Memory Word Size 16 bit 32 bit Access 16 bits 32 bits Storage Little Endian Big Endian

Data Transfer Instructions Advantages Disadvantages Register to Register Simple, faster, constant CPI, Easier to pipeline. Higher instruction count, longer program codes Register to Memory Separate load instruction eliminated, good code density Variable CPI due to different operand locations Memory to Memory Most compact, small number of registers required Variable CPI, variable instruction size, memory bottleneck.

Data Transfer Instructions EAGLE FALCON-A FALCON-E SRC Register to Register a2r, r2a mov lds, sts lar (only from PC) Register to Memory ldacc, stacc load, store ld, st Memory to Memory -

Control Flow Instructions Branches (conditional) Jumps (unconditional) Calls (procedure calls) Returns (procedure returns)

Branch Options Condition Codes Condition Register Compare and Branch test special bits set by ALU specific ordering of instructions required EAGLE uses condition codes for branch condition evaluation Condition Register tests arbitrary registers special register required. none of our processors allocate a specific register for storing branch results. Compare and Branch comparison is part of branch complex all the processors, SRC, FALCON-E, FALCON-A & EAGLE have compare and branch instructions.

Size of Jumps Processor Displacement size EAGLE FALCON-A FALCON-E SRC 8 bits for both conditional and unconditional. FALCON-A FALCON-E 27 bits (unconditional jump), 21 or 32 bits (conditional jumps) SRC 32 bits for both conditional and unconditional jumps. * Although 8 bits displacement seems rather small for large codes, it is generally sufficient since the frequency of instructions using 4 to 8 bit offset from PC is quite high.

Addressing Modes Specify a constant, a register or a location in memory. Common addressing modes are Immediate 123 Register R3 Direct [123] Register Indirect M[R3] Displacement M[R3+123] Relative [PC+123] Indexed or scaled Auto increment/ decrement

Addressing Modes EAGLE FALCON-A FALCON-E SRC Immediate - Direct Register Register Indirect Relative Displacement The register indirect in both FALCON-A and FALCON-E is the special case of displacement addressing mode when constant supplied is zero and the address is taken from the register only.

Size of Displacement Field Processor Number of bits in displacement field SRC 17 or 22 bits depending on the instruction type FALCON-E 21 or 24 bits depending on the instruction type FALCON-A 5 bits for load and store instruction EAGLE 8 bits for ldacc and stacc instructions

Size of Immediate Field Processor Number of bits in the immediate field EAGLE 8 bits FALCON-A 5 or 8 bits FALCON-E 17 or 24 bits depending on the instruction SRC 17 or 22 bits

Similar Instructions (Arithmetic) EAGLE FALCON-A FALCON-E SRC Add add Immediate addi Subtract sub subi - Multiply mul Divide div SRC implements immediate subtraction using addi with a negative constant. Multiply and divide operations in SRC are implemented by multiple shifts and additions.

Similar Instructions (Logic) EAGLE FALCON-A FALCON-E SRC And and Immediate andi Or or ori Not not Neg neg -

Similar Instructions (Shift) EAGLE FALCON-A FALCON-E SRC Shift right shiftr shr immediate - srai Circular shift rol shc Shift left shiftl shl Shift right arithmetic asr sra shra

Similar Instructions (Control) EAGLE FALCON-A FALCON-E SRC No operation nop Halt halt - stop Reset reset

Similar Instructions (Branch) EAGLE FALCON-A FALCON-E SRC Unconditional branch br jump jmp Branch if zero brz jz - brzr Branch if non zero brnz jnz Branch if positive brp jpl brpl Branch if negative brn jmi brmi

Similar Instructions (Calls and Interrupts) EAGLE FALCON-A FALCON-E SRC Procedure call - call brl Interrupt int Interrupt return iret

Similar Instructions (Data Movement) EAGLE FALCON-A FALCON-E SRC Load ldacc load ld Store stacc store st Move mov - Move immediate movi la In in Out out

Instructions Unique to EAGLE EAGLE has a minimal ISA with following unique instructions movia a2r r2a cla

Instructions Unique to FALCON-A ret PC R[ra];

Instructions Unique to FALCON-E push pop ldr str bl bg muli divi xor, xori ror,rori

Instructions Unique to SRC ldr lar str brlnv brlpl brlmi brlzr brlnz

Problem Comparison EAGLE FALCON-A FALCON-E SRC Given is the code for a simple C statement, a=(b-2)+4c and its implementation in all the four processors. EAGLE FALCON-A FALCON-E SRC .org 100 a: .dw 1 .org 200 ldacc b a2r r1 subi r1,2 ldacc c a2r r2 shl r2, 2 r2a r2 add r1 stacc a a: .dw 1 load r1, b subi r2, r1, 2 load r3, c shiftl r3,r3,2 add r4,r2,r3 store r4, a ld r1, b subi r2, r1,2 ld r3, c muli r3,r3, 4 add r4, r3,r2 store r4,a addi r2,r1,-2 shl r3, r3, 2 st r4, a