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Decode and Operand Read
SRC Pipelined Hardware Block Diagram Pipeline Stages Instruction Fetch IR2 PC2 Decode and Operand Read IR3 X3 Y3 MD3 Pipeline Registers ALU Operation IR4 Z4 MD4 Memory Access Z5 IR5 There are also two separate memories and several multiplexers involved in pipeline operation Register Writeback
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SRC Pipeline registers
Between stage 1 and 2 IR2 contains the full instruction PC2 holds the incremented address Between stage 2 and 3 IR3 holds opcode and ra (used in stage 5) X3 holds first operand Y3 holds second operand MD3 holds reg. value to be stored in memory
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SRC pipeline registers
Between stage 3 and 4 IR4 holds opcode and ra Z4 holds result from ALU MD4 holds value to be stored in memory Between stage 4 and 5 IR5 holds opcode and ra Z5 has value to be stored in register
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SRC pipeline stages Stage 1. Instruction fetch
PC incremented or replaced by a new address specified by branch Stage 2. Instruction decode Ld/str get operand for address calculation ALU operations get operand values from registers or constants Stage 3. ALU operation Calculates address or execute arithmetic/logic Br instructions just pass on to next stage
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SRC pipeline stages Stage 4. Memory access Stage 5. Write back
ALU instructions pass data from Z4 to Z5 Ld access memory address given in Z4 Str completes by writing into data memory Stage 5. Write back The contents of Z5 are written to register. It maybe the ALU result, effective address, PC link value or fetched data.
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Decode and Operand Read
ALU Instruction Instruction Memory PC Instruction Fetch Inc4 Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra Decode and Operand Read MUX Mp4 X3 Y3 … decoder ALU Operation ALU Z4 Memory Access Register Writeback
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ALU Instruction … Instruction Memory PC Instruction Fetch Inc4
Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra Decode and Operand Read X3 and Y3 are temporary reg to hold the values between pipeline stages MUX Mp4 X3 Y3 … decoder ALU Operation ALU Z4 Memory Access Register Writeback
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ALU Instruction … Instruction Memory PC Instruction Fetch Inc4
Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra Decode and Operand Read X3 and Y3 are temporary reg to hold the values between pipeline stages MUX Mp4 X3 Y3 ALU computes the result … decoder ALU Operation ALU Z4 Memory Access Register Writeback
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ALU Instruction … Instruction Memory PC Instruction Fetch Inc4
Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra Decode and Operand Read X3 and Y3 are temporary reg to hold the values between pipeline stages MUX Mp4 X3 Y3 ALU computes the result … decoder ALU Operation ALU No memory access for ALU inst. Z4 Memory Access Register Writeback
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ALU Instruction … Instruction Memory PC Instruction Fetch Inc4
Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra Decode and Operand Read X3 and Y3 are temporary reg to hold the values between pipeline stages MUX Mp4 X3 Y3 ALU computes the result … decoder ALU Operation ALU No memory access for ALU inst. Z4 Memory Access Result stored In destination Register Writeback
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Decode and Operand Read
Load/Store Instruction (ld, ldr, st, str) Instruction Memory PC Instruction Fetch Inc4 Op code ra c1 Register File R[rb] R[rc] R[ra] regwrite PC2 Decode and Operand Read MUX Mp4 MUX Mp3 Y3 X3 add … decoder ALU Operation ALU Z4 Data Memory Memory Access Mp5 MUX Z5 Register Writeback
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Decode and Operand Read
Load/Store Instruction (ld, ldr, st, str) Instruction Memory PC Instruction Fetch Inc4 regwrite Op code ra c1 or c2 Register File R[rb] R[rc] R[ra] PC2 c1 or c2 are selected depending on the addressing mode Decode and Operand Read MUX Mp4 MUX Mp3 Y3 X3 … decoder add ALU Operation ALU Z4 Data Memory Memory Access Mp5 MUX Z5 Register Writeback
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Decode and Operand Read
Load/Store Instruction (ld, ldr, st, str) Instruction Memory PC Instruction Fetch Inc4 regwrite Op code ra c1 Register File R[rb] R[rc] R[ra] PC2 c1 or c2 are selected depending on the addressing mode c1 or c2 are selected depending on the addressing mode Decode and Operand Read MUX Mp4 MUX Mp3 Y3 X3 ALU computes the address ALU computes the address add … decoder ALU Operation ALU Z4 Data Memory Memory Access Mp5 MUX Z5 Register Writeback
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Decode and Operand Read
Load/Store Instruction (ld, ldr, st, str) Instruction Memory PC Instruction Fetch Inc4 Register File R[rb] R[rc] R[ra] regwrite Op code ra c1 PC2 c1 or c2 are selected depending on the addressing mode c1 or c2 are selected depending on the addressing mode Decode and Operand Read MUX Mp4 MUX Mp3 Y3 X3 ALU computes the address ALU computes the address add … decoder ALU Operation ALU Store instruction completed Z4 Data Memory Memory Access Mp5 MUX Z5 Register Writeback
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Decode and Operand Read
Load/Store Instruction (ld, ldr, st, str) Instruction Memory PC Instruction Fetch Inc4 Register File R[rb] R[rc] R[ra] regwrite Op code ra c1 PC2 c1 or c2 are selected depending on the addressing mode c1 or c2 are selected depending on the addressing mode Decode and Operand Read MUX Mp4 MUX Mp3 Y3 X3 ALU computes the address ALU computes the address add … decoder ALU Operation ALU Store instruction completed Z4 Data Memory Memory Access Mp5 MUX Z5 Load instruction completed Register Writeback
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Decode and Operand Read
Branch Instruction Instruction Memory MUX PC Instruction Fetch Inc4 Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra PC2 Decode and Operand Read Branch Logic ALU Operation condition Memory Access Register Writeback
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Branch Instruction Instruction Memory MUX PC PC incremented as usual
Instruction Fetch Inc4 Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra PC2 Decode and Operand Read Branch Logic ALU Operation condition Memory Access Register Writeback
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Branch Instruction Instruction Memory MUX PC PC incremented as usual
Instruction Fetch Inc4 Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra PC2 Decode and Operand Read Branch Logic Condition decides new PC value ALU Operation condition Memory Access Register Writeback
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Branch Instruction Instruction Memory MUX PC PC incremented as usual
Instruction Fetch Inc4 Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra PC2 Decode and Operand Read Branch Logic Condition decides new PC value ALU Operation condition No memory access Memory Access Register Writeback
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Branch Instruction PC Inc4 MUX Instruction Memory
PC incremented as usual Instruction Fetch Register File R[rb] R[rc] R[ra] regwrite Op code ••• c2 ra PC2 Decode and Operand Read Branch Logic Condition decides new PC value ALU Operation condition No memory access Memory Access Only brl instructions write register Register Writeback
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The complete pipeline data path
Instruction Memory MUX PC Inc4 IR2 regwrite Register File R[rb] R[rc] R[ra] opcode ra rb rc c PC2 MUX Mp3 Mp2 MUX Mp4 MUX Y3 X3 IR3 MD3 … decoder ALU IR4 Z4 MD4 Data Memory MUX Mp5 IR5 Z5
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Control signals for pipeline stages
branch := br ~ brl cond := (IR2<2..0>=1)~(IR2<2..1>=1)&(IR2<0>^R[rc]=1>))~ ((IR2<2..1>=2)&(!IR2<0>^R[rc]<31>)) sh:=shr~shra~shl~shc alu:=add~addi~sub~neg~and~andi~or~ori~not~sh imm:=addi~andi~ori~(sh&(IR<4…0>!=0)) load:=ld~ldr store:=st~str l-s:=load~ladr~store regwrite:=load~ladr~brl~alu dsp:=ld~st~la rl:=ldr~str~lar
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Control signals for pipeline stages
MP1 (!(branch2&cond):inc4), ((branch2&cond):R1) Instruction Fetch (!store:rc),(store:ra) MP2 MP3 (rl~branch:PC2), (dsp~alu:R1) Decode and Operand Read MP4 ( rl:c1),(dsp~imm:c2),alu&imm!imm:R2) ALU Operation (!load:Z4), (load:mem data) MP5 Memory Access Register Writeback
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CS501 Advanced Computer Architecture
Lecture19 Dr.Noor Muhammad Sheikh
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Review
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Pipelining
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Classification of Instructions
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SRC Pipelining Hardware
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Complete Pipeline data path
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CS501 Advanced Computer Architecture
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