1. Structural RTL for the br and brl instructions
Syntax: brzr rb, rc
Step
RTN
T0-T2
Instruction Fetch T3
CON cond(R[rc]); T4
CON: PC R[rb];
Syntax: brlzr ra, rb, rc
Step
RTN
T0-T2
Instruction Fetch T3
CON cond(R[rc]); T4
CON: R[ra] PC; T5
CON: PC R[rb];

2. Review

3. CS501 Advanced Computer Architecture
Lecture13
Dr.Noor Muhammad Sheikh

4. Structural RTL for the br and brl instructions
Syntax: brzr rb, rc
CON: PC R[rb]; T4
CON cond(R[rc]); T3
Instruction Fetch
T0-T2
RTN
Step
Question: What will be the difference for the br rb, brlnv ra and brl ra, rb instructions ?
Syntax: brlzr ra, rb, rc
CON: R[ra] PC; T4
CON: PC R[rb]; T5
CON cond(R[rc]); T3
Instruction Fetch
T0-T2
RTN
Step

5. Structural RTL for the shr instruction
Syntax: shr ra, rb, c3 OR shr ra, rb, rc
Step
RTN
T0-T2
Instruction fetch T3
n<4..0> IR<4..0>; T4
(N = 0) : (n<4..0> R[rc]<4..0>); T5
C (Nα0) © R[rb]<31..N>; T6
R[ra] C;
Remember:
C3 is the count field, i.e.
C3<4..0>:= IR<4..0>
n represents a 5-bit register; IR bits 0 to 4 are copied into it
N is the decimal value of the number in this register
other instructions that will have similar tables are: shl, shc, shra
e.g., for shra, T5 will have C← (NαR[rb]<31>) © R[rb]<31..N>;

6. A Unibus Data Path Implementation for FALCON-A
<15..0>
holds MSB of dividend
Other ALSU functions R0 R1
16 lines
General purpose registers
(16-bits each) AH A R7
ADD
SUB
ALSU … PC
SHIFTL IR
MAR
MBR CH C
Holds mul and div results
To external CPU bus
Internal processor bus

7. Structural RTL for the sub instruction
Format: sub ra, rb, rc
Step
RTL T0
MAR PC, C PC + 2; T1
MBR M[MAR], PC C; T2
IR MBR; T3
A R[rb]; T4
C A - R[rc]; T5
R[ra] C;
Instruction Fetch
Instruction
Execute
At the end of each sequence, the timing step generator is initialized to T0

8. Needed for the following instructions/operations
ALSU Functions Needed
ALSU Function
Needed for the following instructions/operations
ADD
add, addi
SUB
sub, subi
MUL
mul
DIV
div
AND
and, andi OR
or, ori
NOT
not; applies to the B input of the ALSU
SHIFTL
shiftl
SHIFTR
shiftr
ASR
asr
C=B
to load from the bus directly into C
INC2
to increment the PC by 2; applies to the B input;
assuming a barrel shifter with five n<4..0> signals available as well

9. Structural RTL for the add instruction
Format: add ra, rb, rc
Step
RTL
T0-T2
Instruction fetch T3
A R[rb]; T4
C A + R[rc]; T5
R[ra] C;
other instructions that will have similar tables are:
and, or, sub

10. Structural RTL for the mul instruction
Format: mul ra, rb, rc
Step
RTL
T0-T2
Instruction fetch T3
A R[rb]; T4
CH©C A * R[rc], T5
R[0] CH; T6
R[ra] C;
The FALCON-A mul and div instructions assume unsigned integer operands only

11. Structural RTL for the div instruction
Format: div ra, rb, rc
Step
RTL
T0-T2
Instruction fetch T3
A ← R[rb]; T4
AH ← R[0]; T5
CH ← (AH©A )% R[rc], C ← (AH©A) / R[rc]; T6
R[ra] ← C; T7
R[0] ← CH;

12. Structural RTL for the not instruction
Format: not ra, rb
Step
RTL
T0-T2
Instruction fetch T3
C ← !(R[rb]); T4
R[ra] ← C;

13. Structural RTL for the addi instruction
Format: addi ra, rb, c1
Step
RTL
T0-T2
Instruction fetch T3
A R[rb]; T4
C A + c1(sign extend); T5
R[ra] C;
Sign extension for 5-bit c1 is the same as : (11αIR<4> ©IR<4..0>)
Sign extension for 8-bit c2 is the same as : (8αIR<7> ©IR<7..0>)
other instructions that will have similar tables are:
andi, ori, subi

14. RTL for the load and store instructions Format: store ra, [rb+c1]
Format: load ra, [rb+c1]
Format: store ra, [rb+c1]
Step
RTL for Id
RTL for st
T0-T2
Instruction fetch T3
A R[rb];
A R[rb]; T4
C A + (11αIR<4> ©IR<4..0>);
C A + (11αIR<4> ©IR<4..0>); T5
MAR C;
MAR C; T6
MBR M[MAR];
MBR R [ra]; T7
R[ra] MBR;
M[MAR] MBR;
sign extension of c1
load and store are the same up to step T5

15. Structural RTL for the jump instructions
Format: jz ra, [c2]
Step
RTN
T0-T2
Instruction Fetch T3
CON ← cond(R[ra]); T4
A ← PC; T5
C ← A + c2(sign extend); T6
PC ← C;

16. Recall from pervious lecture
Type II
Op-code ra 8 10 11 15 c2 7
Recall from pervious lecture
…plus four here), plus..
jz (op-code= 19) jump if zero
jz r3, [4] (R[3]=0): PC← PC+ 2;
jnz (op-code= 18) jump if not zero
jnz r4, [variable] (R[4]≠0): PC← PC+ variable;
jpl (op-code= 16) jump if positive
jpl r3, [label] (R[3]≥0): PC ← PC+ (label-PC);
jmi (op-code= 17) jump if negative
jmi r7, [address] (R[7]<0): PC← PC+ address;