1. Processor Organization and Architecture
Module III
Processor Organization and Architecture

2. Instruction Formats Defines the layout of bits in an instruction
Includes opcode & (implicit or explicit) operand(s)
Usually more than one instruction format in an instruction set

3. Common Instruction Formats
Four of them are
Zero-address instruction
One-address instruction
Two-address instruction
Three-address instruction

4. Zero-address instruction
0 (zero) addresses
All addresses implicit
Example: stack
push a
push b
pop c 10

5. One-address instruction
Implicit second address : Usually a register (accumulator)
E.g. Add C // C=C+A(accumulator) 9

6. Two-address instruction
2 addresses
One address doubles as operand and result
a = a + b
Reduces length of instruction
Requires temporary storage to hold some results 8

7. Three-address instruction
3 addresses
Operand 1, Operand 2, Result
a = b + c;
May be a forth - usually implicit
Not common
Needs very long words to hold everything 7

8. Key Design Issues of an Instruction Format

9. Instruction Length Programmers want
More opcodes (to write short programs)
More addressing modes (for flexibility in implementation of certain functions)
Greater address range (more main memory)
This results in longer instruction length (wasteful if 64 bit is used)
Instruction length should be equal to memory transfer length or a multiple of it

10. Allocation of Bits
More opcodes means more bits in the opcode field, which reduces the number of bits available for addressing
Refinement : Variable length opcodes
There is a minimum opcode length but for some opcodes, additional operations are specified by additional bits

11. Instruction Cycle Fetch:
read the next instruction from memory to processor
PC holds the address of the instruction to be fetched
Unless told otherwise, PC is always incremented by 1 after each instruction fetch

12. Instruction Cycle Execute:
Interpret the opcode and perform the indicated operation
The fetched instruction is loaded into IR and performs the required action .
Action falls into any of the following 4 categories
Processor – Memory : Data transfer to/from memory
Processor – I/O : Data transfer to/from I/O
Data Processing
Control : alter the sequence of execution

13. Indirect Cycle
The operand specifier indicates whether an operand need to be fetched from memory which results in indirect addressing.

14. Instruction Cycle

15. A hypothetical machine

17. Instruction Cycle

18. Instruction Cycle State Diagram (without Interrupts)

19. Instruction Cycle State Diagram (without Interrupts)
Address of the next instruction is calculated

20. Instruction Cycle State Diagram (without Interrupts)
Reads instruction from memory

21. Instruction Cycle State Diagram (without Interrupts)
Determines operation & operands to be used

22. Instruction Cycle State Diagram (without Interrupts)
Determines address of operand

23. Instruction Cycle State Diagram (without Interrupts)
Fetch operand from memory or I/O

24. Instruction Cycle State Diagram (without Interrupts)
Perform the operation

25. Instruction Cycle State Diagram (without Interrupts)
Determines address of result

26. Instruction Cycle State Diagram (without Interrupts)
Store result in memory