1. Classification of instructions
4-address instructions
3-address instructions
2-address instructions
1-address instructions
0-address instructions

2. CS501 Advanced Computer Architecture
Lecture02
Dr.Noor Muhammad Sheikh

3. Advanced Computer Architecture

4. Foundation of Computer Architecture

5. Taxonomy of Computer

6. Classes of SA

7. Instruction Set Features

8. Classification of instructions (continued…)
The 4-address instruction specifies the two source operands, the destination operand and the address of the next instruction
4-address instructions are not very common because the next instruction to be executed is sequentially stored next to the current instruction in the memory. Therefore, specifying its address is redundant.
Used in encoding microinstructions in a micro-coded control unit (to be studied later)
op code
source 2
destination
next address
source 1

9. Classification of instructions (continued…)
A 3-address instruction specifies addresses for both operands as well as the result
The address of the next instruction is in the PC
op code
source 2
destination
source 1

10. Classification of instructions (continued…)
A 2-address instruction overwrites one operand with the result
One field serves two purposes
op code
destination
source 1
source 2
A 1-address instruction has a dedicated CPU register, called the accumulator, to hold one operand & the result –No address is needed to specify the accumulator
As you can see, the size of the instruction reduces when the addresses reduce. The length of each field will be much smaller for CPU registers as compared to memory locations because there are a lot more memory locations compared to CPU registers
op code
source 2

11. Classification of instructions (continued…)
A 0-address instruction uses a stack to hold both operands and the result. Operations are performed between the value on the top of the stack TOS) and the second value on the stack (SOS) and the result is stored on the TOS
op code

12. Comparison of instruction formats
As an example assume:
that a single byte is used for the op code
the size of the memory address space is 16 Mbytes
a single addressable memory unit is a byte
Size of operands is 24 bits
Data bus size is 8 bits
A single byte, or an 8-bit, op code can be used to encode up to 256 instructions.
A 16-Mbyte memory address space will require 24-bit memory addresses. We will assume a byte wide memory organization to make this example different from the example in the book.
The size of the address bus will be 24 bits and the size of the data bus will be 8-bits.

13. Comparison of instruction formats (continued…)
We will use the following two parameters to compare the five instruction formats mentioned before
Code size
Has an effect on the storage requirements
Number of memory accesses
Has an effect on execution time

14. 4-address instruction Code size = 1+3+3+3+3 = 13 bytes
op code
source 2
destination
next address
source 1
1 byte
3 bytes
Code size = = 13 bytes
No of bytes accessed from memory
13 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 22 bytes
There is no need to fetch the operand corresponding to the next instruction since it has been brought into the CPU during instruction fetch.

15. 3-address instruction Code size = 1+3+3+3 = 10 bytes
op code
source 2
destination
source 1
1 byte
3 bytes
Code size = = 10 bytes
No of bytes accessed from memory
10 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 19 bytes

16. 2-address instruction Code size = 1+3+3 = 7 bytes
op code
destination
source 1
source 2
1 byte
3 bytes
Code size = = 7 bytes
No of bytes accessed from memory
7 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 16 bytes

17. 1-address instruction Code size = 1+3= 4 bytes
op code
source 2
1 byte
3 bytes
Code size = 1+3= 4 bytes
No of bytes accessed from memory
4 bytes for instruction fetch +
3 bytes for source operand fetch +
0 bytes for storing destination operand
Total = 7 bytes

18. 0-address instruction Code size = 1= 1 bytes
op code
1 byte
Code size = 1= 1 bytes
# of bytes accessed from memory
1 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = bytes

19. Summary

20. Example 2.1 text expression evaluation a = (b+c)*d - e

21. Immediate Addressing Mode
Data for the instruction is part of the instruction itself
No need to calculate any address
Limited range of operands:
for n bit fields, -2^(n-1) to +(2^(n-1)-1)

22. Immediate addressing mode
Example: lda 123 ***
123
Op code
Memory
No memory access needed IR
ACC
data :
*** Note we have used the lda instruction as an example to maintain consistency and to limit the number of operands to one only

23. Direct Addressing mode
Example: lda [123] ***
Opcode
456
Memory .
data
address IR
ACC
123
*** Other asm notations or formats may be used

24. Indirect addressing mode
Example: lda [[123]]
Memory IR
Opcode
Address of pointer
456
123
Address of data :
789
456
ACC
789
data

25. Register (direct) addressing mode (continued…)
Example: lda R2
Op code address of R2
1234
Address of data
data IR R1 R2 R3 R4
ACC
Memory :
No memory access needed

26. Register Indirect Addressing
Example: lda [R1]
Memory IR
Op code
Address of R1
the instruction points to a CPU register
register contains
memory
address R1
123
456
123 R2 R3 R4
CPU Registers
data
ACC
456

27. Displacement Addressing
constant
Example: lda [ R1 + 8 ]
Memory IR
Op code
Address of R1 8
Memory
address
Register address +
Index
456
128
R 1
120
R 2
CPU registers
data
ACC
456

28. Address of the next instruction
Relative Addressing
Example: jump 4
Memory
Opcode IR 4
Address of the next instruction +
Next instruction
124
…... PC
120

29. RISC Stands for Reduced Instruction Set Computers
A concept or philosophy of machine design; not a set of architectural features
Underlying idea is to reduce the number and complexity of instructions
New RISC computers may have some instruction that are quite complex

30. Features of RISC machines
One instruction per clock period
All instructions have the same size
CPU accesses memory only for Load and Store operations
Simple and few addressing modes

31. CISC
Complex Instruction Set Computers

32. Features of CISC machines
More work per instruction
Wide variety of addressing modes
Variable instruction lengths and execution times per instruction
CISC machines attempt to reduce the “semantic gap”

33. Disadvantages of CISC
Clock period, T, cannot be reduced beyond a certain limit
Complex addressing modes delay operand fetch from memory
Difficult to make efficient use of speedup techniques