FEE Electronics progress

Slides:



Advertisements
Similar presentations
Advanced Implantation Detector Array (AIDA): Update & Issues Tom Davinson School of Physics & Astronomy The University of Edinburgh presented by Tom Davinson.
Advertisements

256 channel data acquisition system for VISTA focal plane to readout sixteen 2k x 2k VIRGO detectors Largest ever such system.
Chase Banna Nathan Corwin Robert Scanlon. Problem  Learning to play the guitar can be a very time consuming and frustrating experience.  Without hands-on.
I.Tsurin Liverpool University 08/04/2014Page 1 ATLAS Upgrade Week 2014, Freiburg, April 7-11 I.Tsurin, P.Allport, G.Casse, R.Bates, C. Buttar, Val O'Shea,
High Speed Digital Systems Lab Spring/Winter 2010 Part A final presentation Instructor: Rolf Hilgendorf Students: Elad Mor, Ilya Zavolsky Integration of.
Printed Circuit Board Design
The printed circuit board (PCB) design
Applied Technology High School ATE 1012 Grade 10 Eng. Rose Hasan.
WP7&8 Progress Report ITS Plenary meeting, 23 April 2014 LG, PK, VM, JR Objectives 2014 and current status.
31st July 2008AIDA FEE Report1 AIDA Front end electronics Report July 2008 Progress Virtex5 FPGA choice Milestones for prototype delivery.
AIDA FEE64 production report June 2011 LYCCA tests and MBS Production of FEE64 Preparation for October test. 13th June
9th October 2008AIDA FEE progress report P.J.Coleman-Smith 1 AIDA Frontend Electronics progress report. Mezzanine to FEE64 connection. Mezzanine Layout.
Printed Circuit Board (PCB) manufacture Learning outcomes: To work effectively, independently and in small groups. To understand the importance of personal.
LSU 09/12/2013Electronics - SkeeterSat1 Building SkeeterSat Inventory Components  Identify components Use the parts list and assembly manual  Tape to.
“PCB” -AMIT NIKAM -ASHI NAGARIYA.
FEE Electronics progress Mezzanine manufacture progress FEE64 testing and VHDL progress Test mezzanine. Trial mechanical assembly 10th November 2009.
AIDA FEE64 development report August 2010 Progress after Texas CAD work Manufacturing 25th August
Straw Electronics status and preparation for the technical run NA62 workshop Siena.
12th May 2008AIDA FEE Report1 AIDA Front end electronics Report May 2008 Progress Data compression Plan for prototype delivery.
CMS ECAL End Cap Meeting CERN 19 June to 23 June 2000 A.B.Lodge - RAL 1 ECAL End Cap High Voltage Cards and 2000 Electrical/Thermal Model. Progress on.
Single Board Controller Comments Roger Smith Caltech
Design & test of SciFi FEB
Soldering Dennis Yuan Fall What is it for? Making good conductive contact between a component and the PCB Through-hole parts Surface mount parts.
Update on the HBD Craig Woody BNL DC Meeting June 8, 2005.
27 th September 2007AIDA design meeting. 27 th September 2007AIDA design meeting.
11th March 2008AIDA FEE Report1 AIDA Front end electronics Report February 2008.
Status report on the development of a readout system based on the SALTRO-16 chip Leif Jönsson Lund University LCTPC Collaboration Meeting
FEE Electronics progress PCB layout progress VHDL progress in TBU Prototype fixtures FEE64 commissioning A few of the remaining tasks 16th July 2009.
CSC ME1/1 Upgrade Status of Electronics Design Mikhail Matveev Rice University March 28, 2012.
HBD FEE test result summary + production schedule 16mv test pulse result –5X attenuator + 20:1 resistor divider at input (to reduce the noise on the test.
07-Jan-2010 Jornadas LIP 2010, Braga JC. Da SILVA Electronics systems for the ClearPEM-Sonic scanner José C. DA SILVA, LIP-Lisbon Tagus LIP Group * *J.C.Silva,
TPC Integration P. Colas (thanks to D. Attié, M. Carty, M. Riallot, LC-TPC…) TPC layout(s) Services Power dissipation Endplate thickness and cost Mechanical.
Electronics: Junction Cards, Adapter Card, Purple Card, …. Ron Sidwell, K. Harder, T. Sobering, R. Taylor, E. VonToerne, Kansas State U.
ASIC Activities for the PANDA GSI Peter Wieczorek.
How to make a PCB.
Readout Architecture for MuCh Introduction of MuCh Layout of Much ( proposed several schemes) Read ASIC’s Key features Basic Readout chain ROC Block Diagram.
AIDA FEE64 production report January 2011 Manufacturing Power Supply FEE64 revision A “3 hour test” 19th January
ASSEMBLING THE PCB Have the PCB in front of you as shown. Make sure there are no copper tracks showing. This side is called the component side.
FEE Electronics progress Mezzanine layout progress FEE64 progress FEE64 initial testing Test mezzanine. A few of the remaining tasks 2nd October 2009.
FEE Electronics progress PCB layout 18th March 2009.
ECE 4006B Fall, 2002, Group 1, Mei Chan Progress Report Period (November 22-December 5, 2002) Receive and complete assemble 2 nd PCB board Complete the.
D. Attié, P. Baron, D. Calvet, P. Colas, C. Coquelet, E. Delagnes, R. Joannes, A. Le Coguie, S. Lhenoret, I. Mandjavidze, M. Riallot, E. Zonca TPC Electronics:
Plans to Test HBD Prototype in Run 6 Craig Woody BNL DC Meeting March 8, 2006.
Single Board Controller Comments Roger Smith Caltech
Status of MAPMT FEE Electronics Boards Connector board – have 5 boards, 1 assembled Readout board (“MUX” board) – layout completed 12/2, but unfortunately.
Julie Prast, Calice Electronics Meeting at LAL, June 2008 Status of the DHCAL DIF Detector InterFace Board Sébastien Cap, Julie Prast, Guillaume Vouters.
Saverio MINUTOLITOTEM Electronics W.G., 9 December T1 electronics status.
The printed circuit board (PCB) design §PCB design is part of the design process of a product in electronics industry. §PCB is a piece of insulating plastic.
Electronics Workshop GlueX Collaboration Meeting 28 March 2007 Fast Electronics R. Chris Cuevas Group Leader Jefferson Lab Physics Division Topics: Review.
CCB to OH Interface M.Matveev Rice University February 22,
FEE Electronics progress PCB layout progress VHDL progress in TBU Prototype fixture for software 9th June 2009.
Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.
AIDA: introduction Advanced Implantation Detector Array (AIDA) UK collaboration: University of Edinburgh, University of Liverpool, STFC Daresbury Laboratory.
Flight Computer for IlliniSat-2 Team 12 Mark Mahowald Anuj Pasricha Dan Brackmann 12/9/
Continuity tester a handy tool for testing circuits
Introduction , Variations & Use
SUMMARY OF THE ORSAY LD-TPC ELECTRONICS MEETING
Status of the DHCAL DIF Detector InterFace Board
ELECTRONIC CIRCUIT DESIGN & MANUFACTURE
Test Slab Status CALICE ECAL test slab: what is it all about?
Activities so far Meeting at Imperial, Paul and Matt
TPC Large Prototype Toward 7 Micromegas modules
Assembly order PCB design
पी.सी.बी बोर्ड.
University of California Los Angeles
ECAL Electronics Status
FEE Electronics progress
STAR-CBM Joint Workshop Heidelberg, Physikalisches Institut
FEE Electronics progress
Readout electronics system for Laser TPC prototype
Presentation transcript:

FEE Electronics progress Mezzanine manufacture progress FEE64 testing and VHDL progress 4th December 2009

Mezzanine manufacture Progress PCB manufacturer delayed through the processing due to technically challenging design. Shipped 20 to assembler ( Patronics Ltd ). 15 assembled boards delivered to DL 2/12/09. 5 assembled boards failed final quality control at Patronics. Pads had lifted after re-work. After visual inspection at DL. 10 OK for use. 1 broken track and lifted resistor 1 solder whisker between resistors ( can repair ) 3 solder on ASIC pads Assembled to copper block and found a component fouled. Mechanical workshops removing 0.2mm copper to solve the problem. Creating 5 kits with mezzanine card, mounting pins and copper block with heat conducting foam pad in place for despatch to RAL. 4th December 2009

FEE64 testing and VHDL progress MIDAS control and acquisition system is under development as the VHDL evolves. Spectra taken from all four Mux readout ADCs with reference and input ground. FWHM of 3 channels. 4th December 2009

Clock distribution No further work has taken place. Pcb layout to proceed after VHDL for acquisition complete. Designed for manufacture locally. Master SYNC to clock box FEE64 (sync master) Clock box FEE64 FEE64 FEE64 200Mhz clock and SYNC distribution 4th December 2009