FIT Front End Electronics & Readout   FIT Front End Electronics & Readout V.Kaplin2 , D.Serebryakov 1 , A.Tikhonov1, 1 Institute for Nuclear Research, Academy of Sciences,Russia,Moscow 2 Moscow Engineering Physics Institute,Russia,Moscow

Signal and data flow for “Plan A” 2

Fit electronics variant A

“Plan B” Estimated trigger timing – the same as T0 (one extra stages for averaging, but less delays on cabling CFD DD QTC Scaler Amp 1 12 To TRM Mini-OR Add Mini-OR-A Mini-OR-C TVDC 19 ns TUTO Add A Add C Add Sum Processing modules (18 modules 9U) Trigger module (1) The same as T0 The same as plan A New elements t = 20 ns t = 40 ns t < 100 ns

Mini-OR – Average time calculation between first and last pulses 4 3 1- One detector 2- N detectors with digital averaging 3- N detectors, first selected (T0) 4- N detectors, first selected (FIT) t 1 2 D OR Trailing edge discriminator Leading edge discr. Mean timer 1 2 2´ dt T=10 ns + 10 ps dt MT 5

Fit electronics variant B

Processing module structure Variant A *TDC THS788 also performs on-the-fly delay compensation 7

Processing module structure Variant B

Mezzanine board for connecting to TOF readout 9

Front-End Electronics for the Processing module

Front-End Electronics prototype Installed at P2 Working as part of T0 electronics from 2015

Front-End Electronics channel layout for processing board

1200 MHz interval counter + 64 tap DLL (13 ps/step) TDC THS788 1200 MHz interval counter + 64 tap DLL (13 ps/step)

Multiplicity trigger circuits in the FPGAs in processing and trigger modules (Summing amplitudes from all channels on the detector side and comparing them with thresholds). Updated timings from 190 ns to 170 ns

TVX and OR A/C trigger circuits in the FPGAs in processing and trigger modules. Summing times from all channels, calculating average time per side and comparing them with thresholds). Timings now is calculated for this trigger ~190 ns

FPGA selection: Why Kintex - 7 To fit the LM trigger timing requirements we need to process and send signals with 8*BC =320 MHz frequency. 1. Most complex operation is “adder tree” with 12 inputs, 2 bits pipelined adder, which must process 2 bits every 3.125 ns. For Kintex7 speed grade 2 Xilinx software shows that minimal reachable time for this operation is 2.71ns worst case. This gives reasonable reserve for 3.125 ns requirements. 2. For XC7K160T the estimated usage of the chip slices will be no more than 30 – 40% (Two “adder trees” with all surrounding logic takes 127 slices, there are 24 “adder trees” in the processing module FPGA.) This will take approximately 1500 slices, all other logic can take 2 or three time more slices, so the total estimation is about 6000 slices, this is ~25% of the chip capacity (25350). 3. FFG676 package has 400 I/O with 250 3.3V capable I/O. For processing module we need 12x13 + 4= 156 3.3 V capable I/0 and 3x9+2x12 =51 LVDS pairs (102 I/O lines) for front-end interfacing. We have more than 100 I/O lines for control, clock inputs, etc. remaining. For trigger module we need 20x4 LVDS pairs (160 I/O lines) for trigger inputs from processing modules and 4x20 3.3 lines for control signals to processor modules. This also gives more then 100 additional I/Os for other purposes.

Why not Ultrascale or Ultrascale+ ? Ultrascale has the same speed (661 MHz vs. 650 MHz for K7), but has 1 A quiescent current vs. 40 mA for K7. Ultrascale+ has 20% speed gain (775 MHz vs 650 MHz), but even more quiescent current – 1.6 A. 3. Both families has much more slices for the smallest chips than xck160 chip. This families does not have 3.3 V I/O capability.

Compilation result for 2 12-input pipelined adders (ISE) Design Summary: Number of errors: 0 Number of warnings: 76 Slice Logic Utilization: Number of Slice Registers: 180 out of 202,800 1% Number used as Flip Flops: 180 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 350 out of 101,400 1% Number used as logic: 335 out of 101,400 1% Number using O6 output only: 306 Number using O5 output only: 0 Number using O5 and O6: 29 Number used as ROM: 0 Number used as Memory: 0 out of 35,000 0% Number used exclusively as route-thrus: 15 Number with same-slice register load: 15 Number with same-slice carry load: 0 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 127 out of 25,350 1% Number of LUT Flip Flop pairs used: 385 Number with an unused Flip Flop: 227 out of 385 58% Number with an unused LUT: 35 out of 385 9% Number of fully used LUT-FF pairs: 123 out of 385 31% Number of unique control sets: 6 Number of slice register sites lost to control set restrictions: 4 out of 202,800 1% ---------------------------------------------------------------------------------------------------------- Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score TS_clock = PERIOD TIMEGRP "CLK" 2.74 ns H | SETUP | 0.030ns| 2.710ns| 0| 0 IGH 50% | HOLD | 0.040ns| | 0| 0 All constraints were met.

Simulation result for 2 12-input pipelined adders (iSIM)

Simulation result for 2 10-input pipelined adders (VIVADO) 20

Digital Trigger unit structure

Data format in FE, CRU and FLP FIT solution

Properties of the digitized signals T0+ timing data 11 bits (referenced to BC), 1 LSB = 13 ps, T0+ charge data 12 bits, 1 LSB = 0.25 mV, 1 mip ~ 30 counts V0+ timing data V0+ charge data 12 bits, 1 LSB = 1.25 mV, 1 mip ~ 6 counts This allows to pack 2 channels in 80 bits GBTx word Channel data format: 4 bits reserved 4 bits channel number on board (1-12, 0 – empty) 5 bits reserved 11 bits timing data 1 bit odd/even ADC 3 bits reserved 12 bits charge data Max packet length = 7 (Header + 6 data word for all 12 channels)

System controller unit structure

Readout circuits in the processing module FPGA