1. Integrated Circuits for the INO
Praveen Kumar
Harshit Vaishnav
Nagendra Krishnapura
Indian Institute of Technology, Madras
13th February 2012

2. Integrated Circuits for the INO
Time to digital converter(TDC)
Taped out: Jan 16th
Expected: mid-May
Front end amplifier
Schematic design complete
To do: Layout, post-layout simulations
Analog memory+backend ADC
Preliminary schematic design done
To do: Complete design and integrate with the ADC
Technology used: UMC 0.13mm CMOS

3. TDC specifications Clock period: Tc = 4ns
Fine TDC interval: Tc/32 = 125ps
Fine TDC output: 5 bits
Coarse TDC interval: 215Tc = ms
Coarse TDC output: 15 bits
TDC
range: ms
resolution: 125ps
bits: 20

4. TDC test chip

5. TDC test chip Currently a single-hit TDC Needs reset before next count
Can be adapted to multi-hit
20 bit parallel output

6. TDC architecture
Two fine TDCs to measure start/stop distance to clock edge(T1, T2)
Coarse TDC to count the number of clocks between start and stop(T3)
TDC output = T3+T1-T2
All times normalized to input clock period(4ns)

7. TDC architecture

8. Flash TDC

9. Voltage controlled delay cell

10. Timing logic

11. D flip flop with reduced setup time

12. Coarse TDC, backend Coarse TDC: Synthesized 15 bit counter
Backend: Synthesized arithmetic circuit to compute T3+T1-T2

13. DLL: block diagram

14. Self test circuit

15. Internal and external start/stop/rst

16. Chip layout selftest delay (self test) LVDS Bypass cap. Coarse TDC
Fine TDC
(start/stop)
DLL
Back
end

17. DLL delay nonlinearity

18. DLL locking

19. DLL characteristics

20. TDC: simulated characteristics

21. TDC characteristics

22. Future work Presently designed chip
Delay line/TDC simulation with resistance extracted layout
Test board
Chip testing
Modifications required to this chip
Multi hit capability
SPI interface

23. Analog memory/Amplifier front end
Targetting the next tapeout in mid-April