1. PSD Front-End-Electronics A.Ivashkin, V.Marin (INR, Moscow)
Concept of the FEE
Structure
Functionality
Readout

2. Concept of the PSD electronics:
10 MAPDs/module + T-sensor
11 readout channels
Compact FEE to match with the size of PSD module.
Independent readout of each module.
Motherboard in each module.
Integration with present NA61 DAQ.
Rear side of PSD during MAPD installation

3. All parts are not independent and connected each to others!
Structure of FEE:
Control part - HV MAPD setting with 10 digital resistors, Threshold setting with 1 digital resistor, 1 control amplifier with commutator, LED.
Analog part - 10 amplifier-integrators, 1 signal adder for PSD trigger.
Digital part - 11 ADCs (12-bits, 30 MHz)
Readout part – FPGA Stratix-II with receivers of ADC signals, memory buffer and DAQ interface.
All parts are not independent and connected each to others!

4. Elements of PSD FEE Three parts – three boards Analog part Readout
Digital
Readout
Three parts – three boards
+80V

5. PSD module FEE boards Readout part 3parts -3 boards
FPGA (memory, firmware, DAQ interface), connectors
Digital part
12-bit ADCs, HV-controllers
Analog part (mezzanine board)
10 Integrators, control amplifier, adder for PSD trigger
The most sensitive is analog part. (sensitive to pick-up noise too… unfortunately)
Control amplifier (one for 10 sections) is used for check of MAPD signal at oscilloscope.

6. Control part (Control of MAPD voltages)
Idea
Realization
+80V
+20V
+80V
+20V
One needs two power supplies (+80V and +20V) for all 440 MAPDs in PSD
Also: control amplifier (M~100) with commutator to check the MAPD signals at oscilloscope

7. Analog part Principle of amplifier-integrators (10 per module)
MAPD signal M~5x104
integrated signal M~107
ADC signal
60 ns
300 ns
Adder for PSD trigger (one per module)

8. Time diagram of PSD readout
60 ns
MAPD signal
300 ns
integrator
threshold
Dead time 50 ns
PSD trigger
20 ns
ADC flow 30 MHz
NA61 trigger
~4 ms
Memory 30 MHz
FPGA readout 1.5 MHz
256 words/event/channel
At present, MAPD signals are digitized every 33 ns during ~8.5 ms (256 words).

9. Real ADC signal writen by DAQ
pedestals
signal
8.5 ms
300 ns
Time bin
ADC, ch
5mV periodic noise in pedestals (+ -10 ch) After fit of 10 time bins the width of pedestal is ~1-1.5 channels.

10. Typical pedestals and signals from PSD
Ped. width ~1 ch (RMS)
pedestals
Ped. after fit
signals
Pedestals and signal amplitudes are obtained after the fit of a few ~10 points in corresponding region

11. PSD Module Motherboard
Power
+6V,-6V
+20V, +80V
Address of MB (jumper)
Slow control
DAQ
Trigger
LED
Adder
Amplifier

12. PSD module FEE environment
Concentr.
Board
(2 pieces)
44 cables
Twisted pair ~5 m
SC computer
DAQ
Slow Control
+6V
-6V HV
1 cable Twisted pair ~50 m S
AMP
LED
Trig
oscilloscope
-6V
+6V HV
SC module
LED driver S
LV controller
SC module
Controller
FAN-OUT
CAMAC crate
NIM crate
Signal cable ~50 m
LV crate
Signal cable ~50 m
3 crates at top of PSD
Power logic DAQ Slow cont
NA61 trigger
PSD trigger

13. Conc. Board and CAMAC (Slow control) crate are behind.
+20V power source
Distributor panel with power voltages for all modules
NIM crate with LED driver and trigger modules
Conc. Board and CAMAC (Slow control) crate are behind.

14. Screenshot of one LED event on one PSD module
Current status of FEE
32 modules (~350 readout channels) are running with LED trigger for ~1 week.
4 readout channels were fixed during first days (electronics – science about the contacts).
One channel has strange behavior – low signal (MAPD or cable?).
Screenshot of one LED event on one PSD module
10 sections
T-sensor,
pick-up noise from LED driver

15. PSD trigger (centrality selection based on the energy deposition in PSD)
One needs to sum up the energy from modules.
The gains of MAPDs are equalized within 10-20%.
But light yield of large modules is ~2 times less comparing to small modules. Gain of integrators in large modules is 2 times higher to compensate l.y. drop.
How many modules must be included in sum?
The fragments mainly deposit energy in cental (small) modules.
Shall we include in trigger only central modules?

16. Problems:
Concentrator Boards do not work with Wiener power crate. Separate (uncontrolled) power supply is used now.
HV voltages for MAPDs (+80V, +20V) are also from uncontrolled power supplies – one (+80V) is in small counting room, another one (+20V) is at PSD top.
Waiting for new Wiener HV module. Must be included in Slow Control.
We did not check how PSD trigger is works. Adders are working. One needs to arrange PSD trigger from the beginning.
+80V power supply stands alone in small counting room. It is controlled manually.

17. Thank You

18. Calibration of longitudinal sections by muon beam
2007 SPS beam - 75 GeV l.y~2ph.e/MeV
2010 PS-T10 beam Em<6 GeV l.y~ 6 ph.e./MeV
Remarkable improvement of l.y. due to nice PDE of new MAPDs

19. Geometry and simulation conditions for calibration
PSD Modules:
16 small x10 cm Pb+Scint. (16+4) mm
12 large x20 cm Pb+Scint. (16+4) mm
16 large_new 20x20 cm (Al+Pb+Al)*4+Scin
( )*4 (mm) + 4 mm
For each module the readout is performed in 10 sections (6 Scin in section) →
10 calibration parameters / module
Tree types of modules should be calibrated separately
Modules 13, 38 and 43 were arbitrary chosen for calibration
Calibration was done with 100 GeV protons ( events / module) 19

20. Aj1-10 – amplitudes of the signals in sections 1-10 for event j
Matrix method of energy calibration
T.C.Awes et al., The mid-rapidity calorimeter for the relativistic heavy-ion experiment WA80 at CERN, Nucl. Instr. && Meth. A279 (1989)
Aj1-10 – amplitudes of the signals in sections 1-10 for event j
C1-10 – calibration parameters for sections 1–10 (to be found)
In these calculations we use deposited energy in sections 1-10 as the amplitudes of the signals 20

21. Shape of integrator signal at different frequencies
10 kHz
100 kHz
Analysis part
200 kHz
250 kHz
Shift of pedestal level
Shape is stable but the zero level is shifted – large pedestal (500 ch.) is requested