Mitglied der Helmholtz-Gemeinschaft MicroTCA at the Multiplexing Level of the PANDA STT and the PANDA MVD Harald Kleines, ZEL, Forschungszentrum Jülich

Original Concept in TPR:  Concentrator-Layer  Buffering of Front Data  Optical Serial Links to CNs  Interface to Control System Later Modification:  Multiplexing Layer  Interface to Timing System  New Super Burst Builder Layers  Details not yet defined PANDA DAQ Architecture To Compute Nodes

MicroTCA at the PANDA Multiplexing Layer Central Input for SODA, local distribution on Backplane  Radial clocks TCLA, TCLB or bussed clocks? Performance? Local Uplinks on Concentrator AMCs for high data rate subsystems CPU for management + control system + uplink for low data rate subsystems CPU and Timing AMC should be combined to a dedicated Readout Controller Instead of pure Concentrators also Digitization Modules (ADCs,….) possible AMC: CPU AMC: Timing AMC: Con- centrator 1 AMC: Con- Centrator 2 AMC: Con- Centrator n MCH Backplane 4 Lane PCIe (Point-to-Point to MCH) Clocks, Triggers, Control Signals according to MTCA.4 („uTCA for Physics“) SODA Uplink MicroTCA Crate Optional local Uplinks

Consequences for the Super Burst Building Scalable architecture (Up to 12 AMCs possible) Good Management Support Off-the-shelf commercial components are available Appropriate for smaller lab test systems, too Network and Mechanisms for Super Burst Building undefined, yet Performance Requirements unclear, too MicroTCA Backplane can be part of the Super Burst Building Network Concentrator AMCs can be plugged into Compute Node Version 3 or into ATCA carrier modules  Alternatively, ATCA can be used for Super Burst Building  High degree of scalability Generally more specification of networking, protocols, algorithms, performance requirements,…. for Super Burst Building (+ SODA) required!!!

Concept for PANDA MVD Detector Module Service Board MMB (MVD Multiplexing Board) LVDS GBT:  Serial optical link  3.36 Gb/s (incl. Slow Control)  Under development at CERN (Set of 4 ASICs)  Submission of GBTx (main ASIC) planned in May  Implementation of GBT protocol (Reed-Solomon Encoding) on MMB via FPGA code based on a reference implementation of CERN GBT

PANDA MVD Multiplexing Board (MMB) Pluggable into MicroTCA crate or Compute Node 3 or ATCA carrier SODA could be on the MMB, if backplane performance is not sufficient Details net yet fixed (FPGA-Type,….) 10 Gbit/s Uplink as a first approach, finally a higher multiplexing level is intended Iterative development of Lab Test Systems to approach the final solution (Option) SODA via Backplane

Developed LAB Systems for the TOPIX2 readout Version 1: Dedicated Readout Controller Board  1 Gbit/s optical Link to PC  Implementation of SIS1100 Protocol on Virtex-4 (parallel Interface using SIS1100 OPT) Version 2: Based on the ML605  Implementation of an FMC-Adapter (bigger than FMC due to many connectors)  Identical 1 Gbit/s optical Uplink to PC  Implementation of SIS1100 Protocol on Virtex 6 (using GTX serial transceivers) Mezzanine SIS1100-OPT SIS1100-CMC New Readout Board FMC Adapter ML605

GBT Protocol for Topix3 readout  Intermediate STEP  ML605 in PC (instead of SIS1100)  FPGA Implementation of GBT protocol (on both ML605) GBT Protocol for Topix4 readout  No additional development required (compared to above) Further Developments PC Lab Table GBT Protocol PC GBT Protocol GBT CERN Board TOPIX4 INFN Torino Board E-Link

Development Tasks for GBT protocol on ML605 GBT protocol should be straight forward, based on reference implementation from CERN (Altera Stratix II + Xilinx Virtex-5)  Reference Design successfully ported by Simone Esch (=> see her talk)  Main issue: GTX instead of GTP DMA engine is a major issue  Option: Commercial core Responsibilities:  FPGA-Code: Matthias Drochner  Device Driver: Peter Wüstner PCIe PC ML605 Device Driver Application Software PCIe Endpoint DMA Engine GBT Protocol Mapper GBT Protocol block diagram (CERN)

Development of 10 Gb/s link FPGA: Xilinx XC5VLX30T with FF665 package, well known in ZEL Avoid 10 GigaBit/s on PCB (8B/10B-Codierung => 12,5 GHz)  Use XAUI interface (4 * 2,5 GBit/s)  Use X2 transceiver Modul FTLX8541E2 Synchronization of Vertex5 MGT-Ports?  USE Parallel-to-XAUI SERDES: PM8358, well known from QPACE project In future: Use SFP+ tranceiver

First Protoype: PCIe board Status:  Hardware tests showed serious problems => redesign is going on  FPGA firmware has to be implemented

MicroTCA Board for the 10G optical uplink Status: Design completed Has to be produced Full Size (and Single Width) due to the big X2 transceiver PCIe (4 Lanes) PIC32 I2CI2C div. Signals GbE (Option) XC5VLX30T T.CLOCK A,B PM8358 Finisar FTLX8541E2 SC-connector XAUI (4 x 3,125 Gbit/s) XGMII (32 Bit parallel)

PANDA STT Drift tubes: measurement of drift time (TDCs) Particle Identification => measurement of Energy Loss (dE/dx), too  JU Krakow (for FPC): Time-over-Threshold (with Hades TRB)  ASIC under development at AGH Krakow (Przyborowski,Idzik)  FZ Jülich + IFJ PAN Krakow: Analysis of pulse form + charge measurement/ feature extraction with sampling ADCs + TDCs from WASA  Successful test beam times with discrete preamplifier electronics  No specific ASIC defined, yet (only transimpedance amplifier + low pass filter required) Preamplifier Amplifier/ Shaper Discriminator ADC/QDC TDC FE -Electronics

WASA QDC electronics Free-running sampling ADCs with 12 Bits (cooperation ZEL + Uppsala University) Three versions: 80 MHz, 160 MHz, 240 MHz (LTC2242) History Buffer: 6 µs Mhz) FPGAs – massively parallel computational power in hardware:  Integration  Time stamping  …… list mode option FPGA5 LVD- Bus 16 * Analog in Analog Preprocessing ADC16 ADC15 ADC14 ADC13 FPGA4 ADC4 ADC3 ADC2 ADC1 FPGA1 Discrete preamp from Krakow used during straw tests

Feature Extraction Cluster Structure of Straw Pulses Algorithms implemented in FPGA (W. Erven, FZ Jülich/ZEL)  Baseline restoration  Cluster detection  Pileup detection  Constant Fraction Discriminator  Time measurement (better than 1 ns)  Support Functions for Test Beam Time (Triggering,..)  …… Successful test beam time  8 layers of 16 straws, each P. Kulessa K. Pysz

Developments for PANDA STT MicroTCA 32-channel TDC Based on GPX ASIC Not yet finished (FPGA code,…) Not required anymore  Time resolution of QDC seems ok

Future Developments: MicroTCA QDC Lemo connectors => only 12 channels (additional channels via Rear Module?): OK for test systems Performance considerations:  charge + time + Meta information => about 8 Bytes per hit  Hit rate / channel: up to 1 Mhit/s => 100 MBytes/s per Module  Maximum data rate per crate: less than 10 Gbit/s  10 Gbit/s Uplink is sufficient But: Only 144 Channels/crate => More than 30 crates (expensive!)  Can be reduced to about 15 crates with rear modules Higher connector density => Decisions about cabling required (Noise, distance,….) ! => Consequences regarding ADC chips + analog preprocessing => Consequences regarding space in FPGA for algorithms => Consequences regarding Uplink