1. Mitglied der Helmholtz-Gemeinschaft Juelich Detector Electronics for the Early Phases of the PANDA Detector Development H. Kleines, A. Ackens, M. Drochner, A. Erven, W. Erven, L. Jokhovets, P. Kämmerling, G. Kemmerling, P. Kulessa, H.W. Loevenich, P. Marciniewski, M. Mertens, T. Stockmanns, H. Ohm, S. v. Waasen, P. Wintz, P. Wüstner | Forschungszentrum Jülich

2. Electronics Development Challenges Huge number of detector channels Triggerless DAQ  continuous sampling and readout of detector signals  Event selection needs all detector data  Online event selection by processing entities (FPGA, GPU, CPU,..)  Extreme bandwidth requirements  Technical challenges  New and emerging technologies are required  ASICs in the Front End  Serial backplanes (ATCA, MicroTCA,…)  High speed serial optical links  ………

3. Electronics Developments Restrictions DAQ concepts and interfaces not fully defined or dynamically changing  e.g. Timing System (SODA) New technologies are not really available (e.g CERN GBT chipset) Know how in the partner labs has to be established Lifetime of components (FPGAs,….) is limited  todays developments will be outdated soon and cannot be used as final detector electronics Synergies with other research programs have to be found  e.g. Helmholtz Portfolio “Detector Technologies”  Some challenges are too big for a single lab!

4. Electronics Developments Requirements Electronics required for the test of detector concepts  e.g. sampling of straw signals for cluster analysis and charge measurement Electronics required for the test of detector components  Since more than 5 years, partly with intermediate ASICs  e.g. for the silicon strip readout with the APV25 ASIC (RAL)  e.g. for the silicon pixel readout with the FEI3 ASIC (CERN) Electronics required for the pre-assembly phase  New Challenge: Realistic DAQ electronics setup required for the event filter level  Compute nodes + triggerless free running mode

5. DAQ development approaches in Jülich Use existing DAQ Software  e.g. EMS software for the “Day-1-Experiment” (Beam analysis) Use existing DAQ Modules  e.g. WASA sampling ADCs for Straw Tube signal analysis Develop dedicated test boards Use commercial boards or boards developed in other labs Use FPGA Evaluation Boards  Available for the most recent FPGA families  Complex + a huge variety of external interfaces Iterative developments in order to master new technologies

6. Iterative Developments: MicroTCA / ATCA ATCA: large formfactor, management,…..  High development effort + expensive infrastructure  Intermediate solution: AMC  Labsystems: uTCA AMC-Module ATCA Crate uTCA Crate AMC Carrier *Source: Ganninger + Lenkisch

7. Example: MicroTCA TDC Module 32-channel TDC Mid-size, double width (Fits into mTCA.4 crate) Based on GPX ASIC  Bin size: ~80 ps  Dynamic range: 17 bit  Peak rate/channel: 200 Mhit/s Originally intended for STT readout, but abandoned now, because  focus changed to sampling ADCs  TRB is cheaper for pure timestamping

8. Example: 10 Gb/s optical link PCIe (4 Lanes) XC5VLX30T PM8358 Finisar FTLX8541E2 SC-connector XAUI (4 x 3,125 Gbit/s) XGMII (32 Bit parallel) PCIe module for 10 Gbit/s link to MicroTCA  XAUI interface with PM8358  X2 transceiver Finisar

9. Implementation of the 10 Gbit/s PCIe module Technology change from X2 to SFP+ MicroTCA module available “on the market”  Concentrate on FPGA code

10. Developments for the MVD readout Test board for the readout of Silicon Strip Detectors  Based on the APV25 (RAL)

11. Development of LAB Systems for the TOPIX2/3 readout Version 1: Dedicated Readout Controller Board  1 Gbit/s optical Link to PC  Implementation of SIS1100 Protocol on Virtex-4 (parallel Interface using SIS1100 OPT) Version 2: Based on the ML605  Implementation of an FMC-Adapter (bigger than FMC due to many connectors)  Identical 1 Gbit/s optical Uplink to PC  Implementation of SIS1100 Protocol on Virtex-6 Mezzanine SIS1100-OPT SIS1100-CMC New Readout Board FMC Adapter ML605

12. Switch to Kintex-7  KC705 evaluation board Implementation of SODA on Kintex-7  Talk of Matthias Drochner GBT Protocol on Kintex-7 for Topix4 readout (labsystem) Ongoing Developments PC GBT Protocol GBT CERN Board TOPIX4 INFN Torino Board E-Link

13. Development Tasks for GBT protocol on KC705 Major Effort: FPGA code  PCIe  DMA-Engine: Commercial core?  Mapping???? GBT protocol should be straight forward, based on a reference implementation from CERN PCIe PC KC705 Device Driver Application Software PCIe Endpoint DMA Engine GBT Protocol Mapper GBT Protocol block diagram (CERN)

14. Preparations for the Preassembly Phase: Phase 1 Implement MVD Multiplexing Board with KC705 Focus: FPGA Code Uplink Protocol has to be defined! + Vadatech FMC105 Quad SFP+ Xilinx KC705 =

15. Preparations for the Preassembly Phase: Phase 2 MicroTCA.4 board developed in HGF Portfolio “Detector Technologies” Based on Kintex 7 (4 GTX lanes to Front Panel) Directly usable as MVD Multiplexing Board FPGA code from Phase 1 can be reused HGF-AMC (DESY/KIT)

16. Developments for the PANDA STT Drift tubes: measurement of drift time (TDCs) Particle Identification => measurement of energy loss, too  JU Krakow (for FPC): Time-over-Threshold (with Hades TRB)  ASIC under development at AGH Krakow (Przyborowski,Idzik)  FZ Jülich + IFJ PAN Krakow: Analysis of pulse form + charge measurement/feature extraction with sampling ADCs + TDCs from WASA  Successful test beam times with discrete preamplifier electronics  No ASIC defined, yet Preamplifier Amplifier/ Shaper Discriminator ADC/QDC TDC FE -Electronics

17. WASA QDC electronics Sampling ADCs with 12 Bits (cooperation ZEA-2 + Uppsala University) Three versions: 80 MHz, 160 MHz, 240 MHz (LTC2242) History Buffer: 6 µs (@240 Mhz) FPGAs – massively parallel computational power in hardware:  Integration  Time stamping  …… list mode option FPGA5 LVD- Bus 16 * Analog in Analog Preprocessing ADC16 ADC15 ADC14 ADC13 FPGA4 ADC4 ADC3 ADC2 ADC1 FPGA1 Discrete preamp from Krakow used during straw tests

18. Feature Extraction Cluster Structure of Straw Pulses Algorithms implemented in FPGA (W. Erven, FZ Jülich/ZEL)  Baseline restoration  Cluster detection  Pileup detection  Constant Fraction Discriminator  Time measurement (better than 1 ns)  Support Functions for Test Beam Time (Triggering,..)  …… Successful test beam time  8 layers of 16 straws, each Further improvements going on P. Kulessa K. Pysz

19. Preparations for the Preassembly Phase Implementation of a free running mode Final System: ATCA (large channel number, connector space,….)  Implementation and test of subsampling in order to reduce ADC costs  Development of test board with lower sample rate Intermediate solutions for the preassembly phase possible, e.g. with existing WASA electronics SODA SIS1100 -Protocol Timing + Clock signals WASA Crate KC705 TRBnet