1. GlueX Collaboration Meeting June 3-5, 2013 12GeV Trigger Electronics R. Chris Cuevas 1.Hardware Status  Production Updates 2.DAq and Trigger Testing  Global Trigger Hardware Testing  Implementation Plans 3.Summary

2. All Trigger Modules In Production! 2 Front End Crate FADC250, (FADC125), (F1TDC) Crate Trigger Processor Signal Distribution Trigger Interface Trigger Control/Synchronization Trigger Supervisor Trigger Distribution L1 Trigger ‘Data’ MTP Ribbon Fiber Trigger ‘Link” Control Clock, Sync MTP Ribbon Fiber Global Trigger Crate Sub-System Processor Global Trigger Processor

3. Signal Distribution ( SD )  All production modules have been delivered and passed acceptance!  Nick Nganga has updated the final firmware to include:  Remote FPGA firmware download  Serial Number storage  Recent firmware update for F1TDC test purposes Acceptance test routine development will be used for long term maintenance Software (CODA) library routines complete and included with Full Crate Acceptance Testing (FCAT) – Bryan Moffit SD provides precision low jitter fan-out of 250MHz system clock, trigger and synch signals over VXS backplane to VXS payload modules Latest SD version includes clock jitter attenuation PLL Successfully used 2 SD boards during HPS experiment 3 Trigger Hardware Status Nick Nganga

4. TI – TD Trigger Interface – Trigger Distribution  All production modules have been delivered and pass acceptance  10 TI boards have been modified to be used as TI-”Master” units - TI “Master” mode will allow up to 9 front end crates to be operated from a single TI. Perfect application for several sub-systems. -The Hall D sub-systems can be operated without the Global Trigger/Trigger Supervisor crate -Allows for immediate DAq testing during initial detector installation and commissioning phase -TI-”Master” configuration can remain intact after Global Trigger system is installed. User’s will have option to run from Global Trigger/Sync/Clock or from TI-”Master”  Acceptance test routine development will be used for long term maintenance  Software (CODA) library routines complete and included with Full Crate Acceptance Testing (FCAT) 4 Trigger Hardware Status William Gu

5.  Flash ADC 250Msps ( FADC250 ) - See Fernando’s update Production board delivery to JLAB groups is complete Firmware is stable and includes new “Mode 6” -Readout data includes pulse integral value and time stamp value is high resolution (LSB=62.5ps; 6-bits) -This mode will be used for production Physics operations and will be required for maximum trigger rate Released documentation does not match latest firmware revision, -Firmware is stable now, and will need to be ‘frozen’ so documentation can be reviewed and released -Major firmware revisions unlikely but every firmware change requires software driver routines to be updated. - Will establish firmware change request method and prioritize firmware updates. (FE and DAQ groups) 5 Trigger Hardware Status F. Barbosa H. Dong E. Jastrzembski Jeff Wilson

6. Crate Trigger Processor VXS Connectors Collect serial data from 16 FADC-250 (64Gbps ) Hai Dong Jeff Wilson 2013 Production CTP New Front Panel I/O 6 Crate Trigger Processor ( CTP ) Hall D production quantities (32) awarded to MTEQ in Virginia! 1 st Article board passes acceptance testing! -Production boards expected delivery 22July2013 -Latest Virtex V FPGA parts will support 5 Gbps transfer speed with FADC250 and provide additional FPGA resources for future L1 algorithms Successful operation with HPS calorimeter beam test with latest cluster finding algorithm!! Sixteen FADC250 boards successfully tested in full crate with FCAT application MTP Parallel Optics 8 Gbps to SSP

7. Crate Trigger Processor Level 1 algorithm requirements for Tagger hit pattern has been documented. New ‘scaler’ register requirements have been defined Hall D L1 trigger algorithm for full crate energy sum is stable and is part of FCAT Production version will support higher serial speeds. (5Gbps per ’lane’) Matches V5-FX70T on FADC250, and cost for highest grade Virtex V FPGA is included on production boards. Production version will include front panel I/O (LVDS) Production version will include VXS connection to CPU slot (PPT-17) for development of PCIe interface if needed. Present control/monitoring is via I^2C through Trigger Interface. - Not a high priority and may be moot if CPU does not include VXS Computed crate-level energy sum value sent via 10Gbps fiber optics to Global Trigger Crate (32bits every 4ns) 7 Hai Dong Jeff Wilson A. Somov

8. SubSystem Processor ( SSP )  All production boards have been delivered.  Production contract included: -10 Hall D -15 Hall B -1 each for Halls A & C Acceptance testing is complete and Ben’s test code will be retained for long term maintenance/development.  New FO Transceivers (QSFP) on production boards SSP has been successfully tested with two crate HPS beam test run SSP to GTP serial link definitions have been fully specified and implemented for VXS Initial testing of SSP (Xilinx) => GTP (Altera) Gigabit transceivers is successful  Manages trigger information from up to 8 front end crates. (2048 channels!)  SSP applications are beginning to blossom and these units will be used for a variety of DAq and Trigger solutions 8 Trigger Hardware Status Ben Raydo

9. SSP Prototype – May 2010 Production Status: 1)Schematics & BOM complete  Single FPGA Virtex 5 TX150T  New Fiber Transceivers -- Support 10Gb/s (4 ‘Lanes’) -- Significant cost savings ($40K) A.Assembly contract awarded B.Gerbers are ~100% complete, expecting delivery to vendor by Nov 1 st. C.Parts for 1 st article arrive Oct 17, 2012…1 st article shipment around end of year. ALL Production SSP Delivered and tested Sub-System Processor Status Ben Raydo 8 SSP Production – April 2013 9

10. Global Trigger Processor ( GTP ) (FY – 13) 2 Pre-production GTP modules have been fabricated, assembled and tested thoroughly in Global Test Stand. Interface requirements to SSP and TS have been finalized and tested The GTP transceivers (Altera) have been tested with the SSP at 5Gb/s. Production GTP bare boards received, and inspected Production assembly in progress! 2 production boards expected by mid-June Firmware development and verification activities:  Ethernet interface implemented successfully -- GUI interface uses Root  Implementation of final Physics Trigger equations  Full test of Global Trigger Crate has been a significant effort -See Ben’s talk 10 Trigger Hardware Status Scott Kaneta

11. GLOBAL TRIGGER PROCESSOR (2 Pre-production boards) 4 Channel Fiber RJ45 Ethernet Jack 4x 8-Channel LVPECL Trigger Outputs to TS High Speed Densi-Shield Cable assemblies Altera FPGA Stratix IV GX DDR2 Memory 256 MB Gigabit Links to SSP VXS “Switch” card S. Kaneta 11

12. Global Crate Hardware Testing Global Trigger crate/module testing progressing,,, (Ben will talk next) Cables from GTP to TS have been received and tested. - Densi-shield 8 pair x 4 - 32 Trigger ‘bits’ NOT serialized to eliminate latency. SSP  GTP  TS  TD  TI Verify full trigger system latency Fully qualify SSP  GTP VXS Gigabit transmission Fully qualify GTP  TS interface Measure latency with different global equations Overall latency must be <3.7us Trigger equation development Develop GTP Ethernet User Interface 12 Scott Kaneta Ben Raydo William Gu B. Moffit 2.954us

13. 13 Trigger Hardware Status Trigger Supervisor ( TS ) (FY-11/12/13 activity) Two (2) Pre-production boards have been thoroughly tested 1 st article production version has been received and acceptance testing is successful. 1 st article production board is being used in Global Test Stand for a variety of firmware and CODA library development and test verification. Final CODA library drivers in development Production order for ALL halls is prepared and will be submitted soon  Functional hardware verification with Trigger Distribution (TD) boards complete.  Testing with GTP module is ongoing, and all functions/interfaces have been verified.  New board format from legacy era – VXS Payload module  Distributes precision clock, triggers, and sync to front end crates via the Trigger Distribution modules.  Manages global triggers and ReadOut Controller events William Gu

14. Specification Status VXS and VME64x powered card enclosures ALL crates for ALL Halls: Complete -- One backplane replaced. 2 DIN connectors reversed! -- Power supplies will need response time modification  Excessive PS ripple occurs with full crates  Plan to begin minor modification in June  WIENER reps will provide training for select technical personnel Trigger System Fiber Optics (Q4 – FY13 procurement)  System diagrams have updated for Hall D and Hall B installation  MTP fiber patch panels/cables received for Halls D, B, and C.  Final Trigger Fiber trunk lengths for Hall D & B contingent on cable tray installation 14

15. Summary ALL 12GeV Trigger Modules are in production! Firmware, firmware, firmware, will be iterated and require test verification for:  Tagger “Hit Count” algorithm  SSP and GTP Global Trigger functions  Final TS firmware/functions Further testing at @5Gbps per ‘lane’ for the Global Trigger crate boards will be completed with production GTP Many detector groups are gaining experience with new 12GeV pipeline electronics Acceptance testing activities are complete for delivered production boards. Full Crate Acceptance Test (FCAT) station is developed for FADC250s o Verification of Gigabit serial plus other essential common VXS signaling. Essential CODA library development has been completed Check out 12GeV Trigger hardware progress: https://halldweb1.jlab.org/wiki/index.php/Electronics_Trigger_Meetings https://halldweb1.jlab.org/wiki/index.php/Electronics_Trigger_Meetings Keep up the GREAT progress! 15

16. All sorts of cool stuff

17. TI-1  Trigger Interface module can be configured to control up to 9 front end crates  This method allows for local control of a detector Sub-system.  TI needs to be configured for this mode with multiple FO Transceivers  Local control of CLOCK, SYNC, and Trigger signals  Global Trigger system signals NOT available  Perfect for initial testing of Detector sub-systems. (FCAL, BCAL) Fiber TI operating in TS mode William Gu 5 User Input/Output Front Panel (dECL) TI-2 TI-3 TI-4 TI-5 TI-6 TI-7 TI-8 TI-9

18. Full DAq Crate Testing Plans 17 Before deploying full crates with all required modules: Will test using “Playback” mode and CODA No input cables necessary; User defined signals loaded in front-end FPGA Deterministic test for all channels and Gigabit serial lane alignment check Verify TI  SD  Payload Board Synchronization and Clock Re-Use these tools for Hall commissioning effort Test station used for FINAL firmware verification and software ‘library’ development Bryan Moffit has created a preliminary plan and list of test functions See wiki link  https://halldweb1.jlab.org/wiki/index.php/Full_Crate_Acceptance This full crate test station in EEL109 is an essential infrastructure element needed to test and verify the front end and trigger hardware/software before installation in the Halls. Bryan Moffit Et al.

19. System Description Crate Trigger Processing Flash ADC Modules Detector Signals Sub-System Processing (Multi-Crate) Global Trigger Processing Trigger Supervisor (Distribution) TS -> TD -> TI Link 1.25Gb/s Bi-Directional BUSY Trigger Sync Trig_Comnd CTP -> SSP -> GTP L1 Trig_Data Uni_Directional Energy Sums 6

20. Noise in the FADC (No Readout during data taking) 03/21/2012CniPol Meeting 20 Single Event All Events

21. Noise in the FADC (Readout during data taking) 03/21/2012CniPol Meeting 21 Single Event All Events

22. Two DAQ Crate Testing: FY11 200KHz Trigger Rate! Pre-Production and 1 st article boards have been received and tested Significant effort for circuit board fabrication, assembly and acceptance testing System testing includes: Gigabit serial data alignment 4Gb/s from each slot 64Gb/s to switch slot Crate sum to Global crate @8Gb/s Low jitter clock, synchronization ~1.5ps clock jitter at crate level 4ns Synchronization Trigger rate testing Readout Data rate testing Bit-Error-Rate testing - Need long term test (24 - 48 hrs) Overall Trigger Signal Latency ~ 2.3us (Without GTP and TS) Readout Controller Capable of 110MB/s - Testing shows we are well within limits