6 th Belle PAC, KEK, February 26 and PXD - EVO, 5/March/2012 Ladislav Andricek, MPI für Physik, HLL 1 Belle Physics Belle II: physics, machine, tracking

PXD - EVO, 5/March/2012 Ladislav Andricek, MPI für Physik, HLL 2 Belle II, CDC, PID, ECL, KLM trigger, software.. Tatsuya Nakada (Chair, Lausanne), William Trischuk (Toronto), Yuval Grossman (Cornell), Yoshitaka KUNO (Osaka), Andrey Goloutvin (ITEP), Tomasz Skwarnicki (Syracuse), Niko Neufeld (CERN), Gerhard Buchalla (LMU), Blair Ratcliff (SLAC), Mike Sullivan (SLAC), Marcel Demarteau (Fermilab), Pere Mato (CERN )

PXD - EVO, 5/March/ Ladislav Andricek, MPI für Physik, HLL Main issues (Ushiroda-san) Rotate Belle II or machine? Injection noise: There is very little hope that the machine can help.. our gated DEPFET was very well received!! Thanks to Jan, his measurements came just in time!!

PXD - EVO, 5/March/ Ladislav Andricek, MPI für Physik, HLL Main issues (Ushiroda-san) II machine, IR  report from Accelerator Review Committee ARC  long list of recommendations for the IR  plan B to commission collider rings with IR..  manpower, schedule problems ….

PXD - EVO, 5/March/ Ladislav Andricek, MPI für Physik, HLL Main issues (Ushiroda-san) III PXD (+ TOP …. “both are on the critical path”)

Towards the final production PXD - EVO, 5/March/2012 Ladislav Andricek, MPI für Physik, HLL 6 » wafer floor plan finished  2 L1 ladders, 4 L2 ladders per wafer  48 test matrices and test structures  yield control structures (metallization) » back side implant already done, 150 wafers finished » need 8 wafers, if yield 100% » assume 30%  plan prod. run with 24 wafers » Oct. 2011:  24 of those wafers sent for SOI production  19 DSP SOI wafers received » plan was to start prototype run (PXD9) Feb.2012 » test results from PXD6 devices………………………..……………  pixel design » Physics simulation and mechanical constraints  mechanical envelope and pixel size » experience from PXD6 production  fault tolerant design, technology improvements » System aspects, interconnection ………………………………….  3 rd metal in Cu, bump landing pads on DEPFET substrate  had to stop prototype run because of SOI issue!

New edge trim development at Icemos PXD - EVO, 5/March/2012 Ladislav Andricek, MPI für Physik, HLL 7 » Etching instead of grinding  Technology was up to now not available at Icemos  first tests done early 2011 at another company, had to be discontinued (missing process modules)  Icemos got interested to install this process (and they have the equipment) » Development started end of January 2012  Icemos oxidized top wafers bonded to MPI HLL handle wafers » Status today  mechanical samples finished, small test batch is out for final polish, expect back March 2 » very promising results and fast turn-around (~4 weeks) » next steps  inspection, in-house clean after final polish  if okay, larger batch with pre-processed wafers  time scale: SOI available ~mid May

SOI problem  revised production schedule PXD - EVO, 5/March/2012 Ladislav Andricek, MPI für Physik, HLL d360 d540 d0 d Main aspects of the new schedule: :- no prototyping run, simply no time for it :- start early with main production, as soon as SOI available :- in parallel test projects, with input for production  yield : double metal on full topography  system issues : Cu on PXD6 half-ladders and E-MCM :- if Icemos fails, possible to restart production with SEH SOI with 4-6 months delay  plan B: major risk is that the yield is too low (<30% overall)!  if this becomes true  one layer only at Belle II start and launch a new production mid to late PXD6 half ladder, 50µm thin, 2 wafers ready for Cu flip chipped ASICs  3 DCD/DHP0.2 pairs  4 switchers PXD at KEK, Aug. 2015

PXD - EVO, 5/March/ Ladislav Andricek, MPI für Physik, HLL Plan B and B’ from Onuki-san – striplets and short origami price tag: plan B: 500k€ plan B’: 250k€

PXD - EVO, 5/March/ Ladislav Andricek, MPI für Physik, HLL in summary :- Our new schedule was “not hated” (cite Ushiroda-san) :- the 30min talk was at the end about 60min … a lot of discussion!! :- the gated DEPFET was well received – we have to continue!! :- I think, after some discussions with reviewers and Ushiroda-san, that they understand our strategy much better now: :- start as early as possible with the final production :- in case of yield problems install only one layer DEPFETs :- do system tests with PXD6 half ladders and E-MCM :- mitigate the yield issue with a dedicated test run :- Striplet “Plan B” was presented but I don’t think that this was seen as a serious option :- let’s wait for the written recommendations …..