1. Thinning and Interconnection DEPFET Meeting, Valencia, Sept. 2010 1 Ladislav Andricek, MPI für Physik, HLL  update on thinning  samples for thermal mock-ups  preparations for PXD6 thinning  on module interconnection (3 rd metal layer)  CNM Project  Cu Process at HLL

2. Reminder: thermal and mechanical samples DEPFET Meeting, Valencia, Sept. 2010 2 Ladislav Andricek, MPI für Physik, HLL Goals: -: practice back-etching (50 µ) -: provide samples for thermal mock-ups (integrated heaters …) -: test the micro joint between the half-ladders

3. Micro joint between half-ladders DEPFET Meeting, Valencia, Sept. 2010 3 Ladislav Andricek, MPI für Physik, HLL -: butt-joint between two half-ladders -: reinforced with 3 triangular ceramic inserts at the frame -: about 2x300µm dead area per ladder Very first glued samples  more on that in Martin’s talk (I guess….)

4. Micro joint between half-ladders DEPFET Meeting, Valencia, Sept. 2010 4 Ladislav Andricek, MPI für Physik, HLL gravity effect = Δy/2

5. The issue with laser dicing DEPFET Meeting, Valencia, Sept. 2010 5 Ladislav Andricek, MPI für Physik, HLL -: All (!!) big half-ladders broke during laser dicing   support bar brakes, and the crack goes a few millimeters into the “sensitive” region -: the bigger 1 st layer ladders in one piece are all okay -: the small gluing test samples as well

6. The reason and the cure … DEPFET Meeting, Valencia, Sept. 2010 6 Ladislav Andricek, MPI für Physik, HLL -: 1 st cut on etched side, wafer fully supported -: 2 nd cut on top side, support only in thick area -: if thin area is large compared to supported area  force on thin support bar  stress and break!!! Vacuum Laser 1 st cut Laser 2 nd cut support chuck  Do it the other way around!! The result was impressive: all ladders perfectly cut without losses!! Vacuum Laser 1 st cut support chuck Laser 2 nd cut support chuck

7. Thin Silicon Ladders with heaters - Inventory DEPFET Meeting, Valencia, Sept. 2010 7 Ladislav Andricek, MPI für Physik, HLL Two Wafers are already diced (the mounting holes are unfortunately at the wrong place) : -: a few 1 st layer ladders (no split) have been sent to Carlos M., one more left at HLL -: 2 pairs of 1 st layer and 4 pairs of 2 nd layer half ladders ready to be joined (MPI???) -: 3 wafers left undiced, dicing scheme can be modified to correct for the mounting hole mistake Please contact me, if you need samples for your mock-up!!!

8. Preparations for PXD6 etching DEPFET Meeting, Valencia, Sept. 2010 8 Ladislav Andricek, MPI für Physik, HLL -: Expect first PXD6 Wafers to be ready for back etching next week -: Tests with the PXD6 layout using Al dummy wafer have started -: 5 wafer with PXD6 front side Al prepared -: 2 of those etched from the back side now  We are ready to start with the first PXD6 wafer with the full stack of layers (oxide, 2 poly, nitride, 2 alu..) It will be an exiting week!!! Keep your fingers crossed …

9. DEPFET Meeting, Valencia, Sept. 2010 9 Ladislav Andricek, MPI für Physik, HLL Copper Layer and Interconnection

10. New Project with CNM Barcelona DEPFET Meeting, Valencia, Sept. 2010 10 Ladislav Andricek, MPI für Physik, HLL -: a new project with CNM, Barcelona, (Enric Cabruja) has been started -: project is divided in three parts: I. provide “sensor” samples with two metal layers (Al and Cu) II. ASIC dummies (DCDB and SwitcherB) with eutectic PbSn bumps III. Bump bonding of ASIC dummies to “Sensor” -: work sharing: HLL:  mask design  provide passivated Al samples of both, the Sensor and the ASIC wafers on std. material CNM:  Cu electro-plating of the sensor wafer  bumping of the ASIC wafer  dicing of the wafers and bump bonding of the ASCIs to the sensor substrate -: time line: finish in the first quarter of 2011 -: status: - layout done (together with the XFEL group) - Al lithography of both wafer types (4 sensor and 6 ASIC wafer) finished, - expect BCB passivation to be finished by the end of October

11. “Sensor” and “ASIC” wafer DEPFET Meeting, Valencia, Sept. 2010 11 Ladislav Andricek, MPI für Physik, HLL “sensor” wafer : two second layer half-modules with DCD, SwitcherB and flex cable landing pattern “ASIC” wafer : ~140 bumped DCDB and ~ 140 SwitcherB chips DCDB landing SwitcherB landing Flex lead landing pattern Comb structure Al-Cu “SwitcherB “ “DCDB”  Practice bump bonding, flex attachment, rework, etc. on real size ladders

12. UBM Process and 3 rd Metal Layer at HLL DEPFET Meeting, Valencia, Sept. 2010 1.Sputter Ti:W und Cu (externally at the beginning) 2.Lithography: thick photo resist 3.Thru mask EP: 3-5 um Cu, ca. 2-3 um Sn 4.Resist strip 5.wet etch Cu (FeCl 3, HCl..) 6.wet etch Ti:W: (H 2 O 2 with additives)  Fountain plater for Cu and Sn,  etch baths for seed layer removal,  solvent wet bench Basic processes installed last week! 12 Ladislav Andricek, MPI für Physik, HLL The UBM and 3 rd metal layer are essentially part of the DEPFET production and need to be installed at the HLL!

13. 1 st Cu/Sn Wafer at the HLL DEPFET Meeting, Valencia, Sept. 2010 13 Ladislav Andricek, MPI für Physik, HLL

14. A few numbers.. DEPFET Meeting, Valencia, Sept. 2010 14 Ladislav Andricek, MPI für Physik, HLL -: Cu thickness: 5 µm -: Sn thickness: ~2 µm -: homogeneity over the wafer < 5% -: line/spacing of the traces < 5/5

15. Summary o Fabrication of Belle II PXD thin samples with integrated heaters is finished. Please tell me how many of which type you need. The half ladders are ready for the joining procedure. o Final preparations for PXD6 thinning done, we are ready to receive the first PXD6 wafers for thinning and further processing. o A new project with IMB-CNM was launched. Bumped ASICs (DCD and Switcher) and real size Belle II PXD ladders with Cu landing pads will produced at CNM. CNM also offered to use their flip chip equipment for the bump bonding tests. o The Cu (and Sn) electro-plating line as well as the processes have been installed at HLL with very good first results. The optimization of the process is ongoing. Next steps: o finalize wafers for CNM project o back etching of PXD6, contact etching at the back side and metallization of the back o after some optimization of the Cu-process, the electro-plating line at the HLL will be ready for the production of the first thin Cu-plated ladders. These can then be used to practice bump bonding on the thin material. DEPFET Meeting, Valencia, Sept. 2010 15 Ladislav Andricek, MPI für Physik, HLL

16. Backup slides follow DEPFET Meeting, Valencia, Sept. 2010 16 Ladislav Andricek, MPI für Physik, HLL

17. More tests, some issues, and the next steps DEPFET Meeting, Valencia, Sept. 2010 Contact resistance too high:  4.4 Ω per contact (20 µm diameter) Sheet resistance actually not that bad:  11.8 mΩ/sq for 2.2 µm Cu (measured on various test structures) Bulk resistivity of Cu 1.7µΩcm  ideal sheet resistance for this thickness: 8 mΩ/sq Technology optimization: a.New tests at CNM 2010 b.Install electroplating line at MPI HLL  Understand and solve contact issue  Improve etch process  Optimize annealing process after Cu plating 17 Ladislav Andricek, MPI für Physik, HLL

18. Reverse currents, before and after, both wafer DEPFET Meeting, Valencia, Sept. 2010 PiN diodes on std.. Wafer, 450 µm thick fully depleted Before Copper PiN diodes on SOI Wafer, 50 µm thick fully depleted Before Copper 18 Ladislav Andricek, MPI für Physik, HLL

19. Material budget – measured!! Mass of a 1 st layer ladder including EOS, Si only: 1.10 g Mass of a 2nd layer ladder including EOS, Si only: 1.24 g Mass in the sensitive region only, 1 st layer, 90x15 mm 2 :0.36 g ρ Si =2.33 g/cm 3  eq. Si thickness in sensitive area:120 µm X 0 (Si)=9.36 cm  Radiation length in the 1 st layer:0.125 %X 0 (Silicon only) TDR: 0.164 %X 0 (50 µm top, 450 µm frame) TDR says: sensitive region:0.053 % silicon frame:0.076 % ------------ 0.129 % The rest are the Switchers, copper layer, and bumps.. DEPFET Meeting, Valencia, Sept. 2010 19 Ladislav Andricek, MPI für Physik, HLL

20. Alu resistors on thin Silicon – a closer look DEPFET Meeting, Valencia, Sept. 2010 20 Ladislav Andricek, MPI für Physik, HLL -: Three regions with separate biasing of resistors Per half-ladder: 1: thinned sensitive region 6x900 Ω (L1) 8x900 Ω (L2) 2: Switcher 6x250 Ω 3: DCD/DHP Region 1xR175 Ω -: One common line per half-ladder -: off-ladder connection at thick EOS via thin wire attached with Ag adhesive -: wafers ready for dicing this week Thin area

21. Why Copper? -: There are three types of ASICS on the ladder: DCD (UMC, 0.18), DHP (IBM, 90nm), and Switcher (AMS-HV, 0.35) -: Interconnection ASICs-Sensor by bump bonds (solder bumps, SnAg and SnAgCu) DCD and DHP will be delivered with bumps (pitch ~200 µm), Switcher is bumped in-house at Uni Heidelberg on chip level (solder jetting) -: for the bump bond process we need a solderable landing pad on the sensor substrate  install Cu/Sn process at HLL -: Bump bonding (flip chip) will then be done at Uni Heidelberg and/or CNM (Barcelona) -: the Cu layer is effectively a 3 rd metal on the sensor – ρ(Cu) / ρ(Al) ≈ 0.63  low impedance wiring layer and additional routing freedom (C. Kreidl, Uni Heidelberg) DEPFET Meeting, Valencia, Sept. 2010 21 Ladislav Andricek, MPI für Physik, HLL

22. Reminder: thin mechanical samples o on mechanical grade SOI Wafers, no electrical functionally o for mechanical and thermal studies and evaluation of micro-joint  fully Al coated on top wafer, back-thinned 50 micron top, Belle-II PXD layout  Al layer structured  resistors as heaters …. 90 28 61,78 DEPFET Meeting, Valencia, Sept. 2010 22 Ladislav Andricek, MPI für Physik, HLL