1. Thinning and Plans for SuperBelle
5/14/2018
Thinning and Plans for SuperBelle
-: Where we are
-: SuperBelle Module and Radiation Length
-: To-do-list for the next Production
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

2. Large area diodes and mechanical samples
5/14/2018
Large area diodes and mechanical samples
Alignment marks
in BOX to find the
partial p-implant
after bonding
IR photo: 80 nm step in BOX
4 "full size" 1st layer ILC ladders
100x13 mm2, 1 and 3 mm frame
along the long side
Diodes with
various areas
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

3. Large area diodes - characteristics
5/14/2018
Large area diodes - characteristics
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

4. Large area diodes - characteristics
5/14/2018
Large area diodes - characteristics
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

5. Large area diodes - characteristics
5/14/2018
Large area diodes - characteristics
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

6. Large area diodes - characteristics
5/14/2018
Large area diodes - characteristics
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

7. SuperBelle Module Still some open questions (among others..):
5/14/2018
SuperBelle Module
Still some open questions (among others..):
1. How thick is the frame?
2. Need the Switchers to be thinned?
3. How large has the end of the ladder to be? Hans
4. Circuitery at the ladder end:
Two Alu layers enough? Passive components?
How to attach them? Connectors or direct
flex lead attachment?....
urgent task for the "module group":
- Sensor technology
- ASIC designer
- Hybrid designer
next slide
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

8. SuperBelle Module  Material Assesment
5/14/2018
SuperBelle Module  Material Assesment
 Switchers or frame or both need to be thinned
-: frame thinning: on chip or wafer level, post-processing (grinding) at IZM Munich  tests to start soon!
-: Switcher thinning: on chip level difficult, but possible (SimbolX HED did it)  service provided by CMP
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

9. PXD6  on SOI Wafer  first thin DEPFETs 
5/14/2018
PXD6  on SOI Wafer  first thin DEPFETs 
-: Thinning technology has now to be implemented into the DEPFET process!
-: Top and Handle Wafer ordered  delivery in 4 weeks from now!
Next steps:
-: Define as fast as possible DEPFET chip sizes and arrangement on the wafer!!!
 need of pre-processing before SOI production (oxidation, back side implant)
 since already in PXD6 we will have MCM modules with DCD and possibly
DHP at the ladder end, we need as soon as possible at least an estimate
of the space requirements! The actual layout can follow later....
-: SOI production TRACIT/Soitec (50 µm top layer, Handle Wafer 400 µm), ~6-8 weeks ARO
 need to submit the wafers end of November in order to have the SOIs ready
for the PXD6 prod.
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

10. Backup slides follow….
Ladislav Andricek, MPI fuer Physik, HLL

11. PiN Diodes on thin Silicon
5/14/2018
PiN Diodes on thin Silicon
CV Curve: depletion at 50 V Al
ρ ≈150 Ω.cm
IV Curve: Irev<8pA at 50 V
20 diodes  Irev(50 V): <100pA/cm2
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich

12. Thinning Technology Compatibility with the main production line tested
5/14/2018
Thinning Technology
Top Wafer
Handle <100> Wafer
a) oxidation and back side implant of top wafer
b) wafer bonding and grinding/polishing of top wafer
c) process  passivation
open backside passivation
d) anisotropic deep etching opens "windows" in handle wafer
Compatibility with the main production line tested
So far:
-: mechanical samples
-: test structures (diodes) on SOI wafers
The technology found its way into other projects:
-: production of thin (75 and 150 μm) ATLAS pixel sensors for sLHC
-: first production of Geiger-mode APDs on 70 μm top layer
Ladislav Andricek, MPI fuer Physik, HLL
Ladislav Andricek, MPI Munich