October 12th 2005 ICALEPCS 2005D.Charlet The SPECS field bus  Global description  Module description Master Slave Mezzanine  Implementation  Link development  Software  Evolution and conclusion

ICALPCS 2005 D.Charlet LHCb detector 32 Links 26 Links 25 Links 80 Links 17 Links

ICALPCS 2005 D.Charlet Why SPECS   LHCb requirement Configuration system for individual boards located on the detector or in the crates located in the cavern. Located in radiation sensitive environment, up to 20kRads. Long distance link, > 100m. Multi configuration (multi-drop bus, point to point). Multi standard interfaces (JTAG, I2C, parallel bus, ctrl I/O). Cheap and compact standard. Can make use of standard Ethernet cables. Safe, fast and clean communication. A Serial Protocol for Experiment Control System

ICALPCS 2005 D.Charlet SPECS architecture   Mono-master multi-slave bus.   Bi-directional, serial, synchronous bus.   Differential link   Ethernet cable and connectors.   Master base on PCI bus.

ICALPCS 2005 D.Charlet Frame description

ICALPCS 2005 D.Charlet SPECS system

ICALPCS 2005 D.Charlet PCI Specs master board   PCI standard: 3.3V 32-bit 33 MHz   Includes: 4 SPECS masters, 1 slave for on board test   I2C and JTAG facilities   PCI bus interface: PLX9030 standard chip   SPECS system: integrated in EPC1C12 CYCLONE ALTERA FPGA   SPECS link: Driver from B-LVDS family DS92LV090 and pole-zero cancellation Receiver SN65LVDS032 High common mode range

ICALPCS 2005 D.Charlet SPECS-master FPGA block diagram

ICALPCS 2005 D.Charlet SPECS master board (PCI)

ICALPCS 2005 D.Charlet SPECS system

ICALPCS 2005 D.Charlet SPECS slave functions Features of slave:  SPECS bus: Point to point slave interface Point to point slave interface Multi drop Multi drop  Parallel interface: Parallel bus (16 data, Parallel bus (16 data, 8 address) 32 configurable I/O lines 32 configurable I/O lines  Serial interface: Long distance I2C bus Long distance I2C bus On board I2C bus On board I2C bus JTAG bus JTAG bus 16 receiver enable 16 receiver enable 16 driver enable 16 driver enable  Interrupt: User interrupt User interrupt Transmission error  Channel B decoding: L1 rst, L0 rst, L1evt_rst, B_calib L1 rst, L0 rst, L1evt_rst, B_calib  Serial EEPROM interface: Identification register Identification register User register User register

ICALPCS 2005 D.Charlet SPECS receiver logics design No external Clock required.  No I2C/JTAG master included in the slave  One SPECS byte -> - one JTAG cycle. - one JTAG cycle. - one I2C bit. - one I2C bit. Parallel access TCK=0 Start condition = Reset logics SCL Data latching Function decoding Cmd Data Shift register SDA SCL SDA SCL=0 SDA SCL=1 SDA SCL=1 SDA SCL=0 I2C SDA SCL TDI TMS TRst TCK=1 TDI TMS TRst JTAG

ICALPCS 2005 D.Charlet SPECS system

ICALPCS 2005 D.Charlet SPECS slave mezzanine Features of Mezzanine same as those of slave. All functionalities provided through 2 SMC connectors.  Driver for point-to-point SPECS bus.  Local oscillator.  Serial PROM.  Power regulator.  Local address switch.  ADC with 6 analog inputs (DCU chip from CERN ME group)  FPGA APEX20K60 82mm 58mm

ICALPCS 2005 D.Charlet SPECS slave mezzanine

ICALPCS 2005 D.Charlet Radiation hardness ComponentTest conditionTotal dose FPGA APABy company40Krads DS92LV010LAL (Ganil)> 28,8KRads SN65LVDS032LAL (PSI)> 147KRads DCU (ADC)CMS> 100KRads PROM AT17LV65LAL (Ganil)> 28,8KRads Transistor NE805ATLAS> 125KRads  SEL  Test of all exposed components Depends on the specific sub-detector. Vertex sub-detector is the most exposed 30KRads  SEU  Logic design uses triple voting technique.  Total dose depends on the location  Maximum of 30kRads  Below the limits of the components as shown above.

ICALPCS 2005 D.Charlet Mezzanine implementation

ICALPCS 2005 D.Charlet Mezzanine implementation (Calorimeter)

ICALPCS 2005 D.Charlet Link architecture RJ45 Patch panel MEZZANINE DS92LV010 10uH 82Ohm DS92LV010 RJ Ohm SN65LVDS32 100nf 50Ohm DS92LVD090 RJ nf51Ohm 2.2nf 51OhmMASTER RJ45 100m RJ45RJ45 5m 25m   B-LVDS driver with high output current (10mA)   Receiver with high common mode voltage range (-2v to 4.4v)   Low differential input thresholds (<50mv)   Ethernet cat6 cable and shielded RJ45 plugs   Pole-zero cancellation

ICALPCS 2005 D.Charlet Output signal from Master SN65LVDS32 100nf 50Ohm DS92LVD090 RJ nf51Ohm 2.2nf 51OhmMASTER

ICALPCS 2005 D.Charlet Signal at Slave input (without pole zero) MEZZANINE DS92LV010 10uH 82Ohm DS92LV010 RJ Ohm Test with 100m and 2 patch panels

ICALPCS 2005 D.Charlet Signal at Slave input (with pole zero) MEZZANINE DS92LV010 10uH 82Ohm DS92LV010 RJ Ohm Test with 100m and 2 patch panels

ICALPCS 2005 D.CharletSoftware All tools have been developed for both Windows and Linux   3 different software levels: PCI drivers: developed by the PLX Company, they enable the communication with the PLX9030 chip on the SPECS master board via the PCI bus SpecsLib library: computes the different frames for all types of mezzanine access (Parallel, I2C, JTAG,...), for write and read operations. SpecsUser library: decodes the frames into useful data values, manages the status for the PCI accesses, also handles the more complex accesses like JTAG, I2C, DMA, and communications with the on-board ADC (DCU).   All these components interfaced with the PVSS software

ICALPCS 2005 D.Charlet Example of PVSS display

ICALPCS 2005 D.Charlet Remaining work and conclusion   Remaining work on Master 20 masters have been produced, tested and distributed to the SPECS users ~50 more will be provided for the commissioning.   Remaining work on Slave A rad-tolerant version is being developed based on the ACTEL PRO ASIC family (APA150) 30 slaves have been produced, tested and distributed to the SPECS users ~300 slaves (new version) will be provided for the commissioning.   Conclusion A 10Mbit/s serial field bus has been designed for LHCb experiment. Its aim is to be simple, cheap, reliable and to work safely in radiation sensitive environments. It is mainly used to download and read back the configuration of the electronics located on the detector. It is made of Master PCI boards and slave daughter boards, provides I2C, JTAG and parallel interfaces for the users, and is delivered with a software patch.

ICALPCS 2005 D.Charlet Multi-drop model analysis   Logic Standard: B-LVDS   Termination resistor: 45 Ohms   Differential line impedance: 100 Ohms   Transmission line: differential stripline   Length of line: 40 cm   Frequency: 40 MHz   Number of stubs : 21   Ibis model: I/O DS92LV090

ICALPCS 2005 D.Charlet Multi-drop simulation result 13th slot 1st slot