1. New service board SYSTEM OVERVIEW AND nSB BOARD ARCHITECTURE LHCb Italia Collaboration Meeting Valerio Bocci, Paolo Fresch

2. Index: 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE2 I.Introduction II.nSB architecture III.nSB board architecture IV.nSB board review V.e-link bus VI.Theoretical speed and I2C FM+ test VII.Schematic Diagrams status VIII.Open questions and future development

3. Introduction System Overview: 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE3 nPDM nSB IGLOO2 FPGA ECS room (on-line PC) BACKPLANE FE chain (max 8 boards) … (up to 12 chains) 20 e-link @ 80 Mbps 1 e-link @80 Mbps Up to 20 per crate Up to 1 per crate LDVS BUS

4. nSB main architecture and features 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE4  Complete and direct accesso to FE via GBT system (12 parallel protocol converter)  Auxiliary external full access to FE  Remote and local FPGA microprogramming on-board (plus SPI connected but unused)  FPGA internal FF(s) protected by TMR redundancy (SEU tolerant)  Possibility to activate built-in EDAC system (Microsemi® CoreEDAC)  FE test_pulse generation configurable via I2C  Specific Power modules  State-of-the-art reset modules  Available fabric for additive features Power and Reset Module

5. nSB board architecture 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE5 I2C LVDS TST_PLS RESET SCnx SDnx SDBp all LVDS RJ10 (x12) … RJ10 BANK Front-End Boards FPGA IGLOO2 GBT SCA CK NET >40 MHz CK NET >40 MHz nSB SN STORAGE 8 POWER MODULES RESET MANAGER 3V3 1V5 1V2 nBackpalne CLK DTX DRX E-link SCL SDA AUX I2C PORT 5V0 PWR_GOOD I/O X 12 COMM_I2C_LVDS I/O LVDS INTERFACE (BANK 2/4) GLOBAL_AUX_I2C LHC_40 MHz BC_PULSE LHC_40 MHz both LVDS COMM_I2C LVDS INT (BANK ?) I2C Master 4 CORE_ALARM ALARMS 12 AUX_JTAG JTAG header AUX LOCAL I2C I2C header (8 pin) LOCAL_CTRL_I2C X 12 I2C Master JTAG Master 1V5_PWR_EN 2 1V2/3V3_PWR_EN I/O CURR_SENS ADC 3/6 FE_CHAIN_RESET DEVRES_n I/O SCA_RESET JTAG uProg PORT MSIO 3V3 (BANK 1) MSIO ?? 2 2 2 5 SN crate slot 5 SN_crate_slot

6. nSB board review The main architecture and functionalities have been approved during the last EDR at CERN but some little modifications are required: 1.FE RESET lines pass through the SCA to prevent malfunctions due to coding errors 2.Online uProgramming of the FPGA is not required but it will be possible 3.SCA GPIO can be sourced with 2V5 module. Migrating from CMOS 3V3 logic to CMOS 2V5. Now FPGA, FE and SCA has the same voltage levels 4.External RESET MANAGER is not required. It is built in in SCA and IGLOO2 5.Special circuit to retain the reset signals of SCA and FPGA on power up implemented. Derived from VLDB. It uses the PGOOD signal from FEASTMP_CP modules 6.Special VME connector to carry the 80 Mbps e-links are under investigation. Signal integrity simulations and test scheduled, starting from the begin of next year. 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE6

7. nSB board review 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE7 I2C LVDS TST_PLS RESET SCnx SDnx SDBp all LVDS RJ10 (x12) … RJ10 BANK Front-End Boards FPGA IGLOO2 GBT SCA CK NET >40 MHz CK NET >40 MHz nSB SN STORAGE POWER MODULES AND RESET CTRL (FEASTMP_CP) 2V5 1V5 1V2 nBackpalne CLK DTX DRX E-link SCL SDA AUX I2C PORT 5V0 PWR_GOOD I/O X 12 COMM_I2C_LVDS I/O LVDS INTERFACE (BANK 2/4) GLOBAL_AUX_I2C LHC_40 MHz BC_PULSE LHC_40 MHz both LVDS COMM_I2C LVDS INT (BANK ?) I2C Master 4 CORE_ALARM ALARMS 12 FRONT HDMI LOCAL_CTRL_I2C X 12 I2C Master JTAG Master 1V5_PWR_EN 1V2_PWR_EN I/O CURR_SENS ADC 3/6 FE_CHAIN_RESET DEVRES_n I/O SCA_RESET JTAG uProg PORT MSIO 3V3 (BANK 1) MSIO ?? 2 2 2 5 SN crate slot 5 SN_crate_slot FE_CHAIN_RESET 2 LDVS BUS FRONT HDMI

8. e-link bus 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE8

9. Theoretical speed and I2C FM+ test 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE9  The e-link communication speed is limited by the BGT-SCA chip @ 80 Mbps  For a complete write cycle 2 different CMD are required (not possible to use the single byte write operation)  For similar reasons 3 different CMD are required for a complete read cycle WORST PAYLOAD: separate e-link packets used

10. Theoretical speed and I2C FM+ test 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE10 It is clear that even in the worst case (single e-link packet/SCA command) the e-link protocol should be able to drive the 12 I2CLVDS ports in parallel. The bottleneck is the FM+ of the GBT SCA module.

11. Theoretical speed and I2C FM+ test Is the Protocol converter able to drive the DIALOG at 1 MHz?? 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE11 Protocol Converter IGLOO2 FPGA evalboard FE (DIALOG) Standard I2C Master Arduino Due FE (DIALOG) FE (DIALOG) … SCL SDA SCnx SDnx SDBp FE daisy chain ( max 8 FEs) In the Roma1 LabE some tests on the logic of the converter have been done to make sure that a standard I2C FM+ master is able to write and read the DIALOG registers

12. Theoretical speed and I2C FM+ test 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE12 Arduino DUE/YUN is not able to drive I2C FM+ but… 1.It is easy to program thanks to its built-in library for different applications (Ethernet, I2C, ecc…) 2.It is easy to find, cheap and versatile. It manages slower versions of I2C For this reasons we decided to use it for speed tests and we are thinking to employ it as well for automated test on production and as a portable test device (accessing the nSB, nPDM and the FE through the AUX I2C port): AUX I2C PORT USB Wi-FI NB: moreover we discovered that overcoming cross-talking and resonance effects (with a LPF) it has been shown that it is possible to use arduino for I2C FM+!

13. Theoretical speed and I2C FM+ test 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE13 Adding a low-pass filter on the bus limits the bandwidth, improves the SNR and eliminates spurious glitches (the I2C protocol requires the suppression of glitches shorter than 50 ns). Moreover enables the communication with Arduino devices and makes the system able to work at even higher speeds thanks to a controlled bus capacitance. A special attention will be given on this aspect of the bus, employing EDA tools also. #nofilter#filter on SCL #filter on both @ 1 MHz

14. Schematic Diagrams status 05/12/2015 P. FRESCH, INFN ROMA1 – LHCB UPGRADE14 Thanks to the constant and qualified support of the LabE team (in the person of G. Chiodi) most of the schematic diagrams are ready for the wire routing step. Just some little modifications are required (i.e. the I2C bus filter under test and simulation and the e-link connectors).

15. Thank you FOR YOUR ATTENTION!