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Computer Architecture Lecture10: Input/output devices Piotr Bilski.

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1 Computer Architecture Lecture10: Input/output devices Piotr Bilski

2 Communication with input/output devices Device is connected with the system bus by the I/O module Speed of the devices and the bus is different – a bridge may be needed! Data formats in the computer system are different for the CPU and I/O devices are different

3 I/O module scheme Input/output module Control lines Data lines Address lines Peripherial device

4 External devices for human communication (monitor, printer) for machine communication (CD drive) for remote communication (modem, network interface)

5 Peripherial device scheme Logical control units Buffer Converter I/O external data I/O module data Input/output module Control signals State signals

6 Peripherial devices speed

7 Input/output module control and timing CPU communication device communication data buffering error detection Classification:

8 Communication between CPU and module instruction decoding data transfer state information transfer address identification

9 Cooperation between CPU and peripherial device CPU requires device state I/O module sends information about device state if device is working, CPU sends data transfer request I/O module receives data unit from the peripherial device and sends to CPU

10 Input/output module scheme

11 I/O modules types Input/output channel – more complex, performs most of the work related to the communication and device handling (mainframe computers) Device driver – simple, most of the functions are performed by the software (personal computers)

12 Input/output techniques Programmable input/output – high processor load Interrupt driven input/output – low processor load Direct memory access – processor is not required

13 Programmable input/output CPU sends I/O instructions to the module. It must control read/write process (when output data are accessible?) Instructions fetched from the memory are mapped into the instructions sent to the I/O module Disadvantage: processor idle most of the time

14 Input/output instructions control (specific for the particular devices) testing (device state and result of the last operation) read write

15 Programmable input/output scheme Sending read instru- ction to the module Reading word for I/O module State? Reading I/O module state Writing word into memory Execution? YES NO Not ready Error handling Ready CPU  I/O I/O  CPU CPU  I/O Next instruction

16 Input/output instructions I/O devices addressing problem: a)Memory mapped I/O b)Isolated input/output 200 Load AC 1 201 Store AC 517 202 Load AC 517 203 Branch if St=0 202 204 Load AC 516 200 Start I/O 5 201 Test I/O 5 203 Branch if St=0 201 204 In 5 (a) (b)

17 Interrupt-driven Input/output CPU sends requests to the I/O module, but does not wait for the response when module is ready to communicate with CPU, raises interrupt signal CPU in every instruction cycle checks if the interrupt was raised disadvantage: CPU communicates between peripherials and memory

18 Interrupt handling scheme Send read instru- ction to the module Read word from I/O module State? Read I/O module state Writing word into memory Execution? YES NO Error handling Ready CPU  I/O I/O  CPU CPU  I/O Next instruction CPU does something different interrupt!!!!

19 Interrupt handling details Device driver raises interrupt CPU ends instruction execution CPU signals interrupt confirmation CPU puts PSW and PC on the stack CPU loads new PC value (interrupt handling) Saving informations about the process state Interrupt handling Restoring information about the process state Restoring PSW and PC software hardware

20 Multiple devices handling problem multiple interrupt lines Software poll Hardware poll bus master (PCI, SCSI) I/O module Interrupt lines devices connections

21 Daisy chain module signalizes raising interrupt putting a vector on the data bus bus terminator Module 1 Module 2

22 Interrupt controller Intel 82C59A CPU 386 INTR INTA Master interrupt controller 82C59 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 INT Slave interrupt controller 82C59 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 INT IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 INT Slave interrupt controller 82C59 Device no 1 Device no 2 with priorities rotational maskable

23 ISA bus interrupt system Two chained 8259 modules Connection with modules is performed through IRQ 2 IRQ 9 is used to redirect requests to IRQ 2 15 interrupt lines to the chain

24 Programmable interface for the peripherial devices Intel 82C55A I/O module used by the 80386 processor Module programmable by the control register (versatility) 40 signal lines: –24 input/output lines –8 data lines (bits) –2 address lines

25 82C55A module scheme

26 Direct memory access (DMA) Allows to transfer large amounts of data to/from memory without bothering CPU Faster than interrupt-driven communication

27 DMA module scheme Memory module „pretends” to be CPU (cycle stealing) Data counter Data register Address register Control logic circuits Data l,ines Address lines DMA REQ DMA ACK INTR READ WRITE

28 DMA work regime informations requested by the CPU from the DMA controller: –Read or write –Peripherial device address –First memory cell address to read/write –Number of the words for read/write CPU executes subsequent program instructions DMA controller controls the flow of information between the peripherials and memory When the task is finished, the controller raises interrupt

29 DMA control points Instruction fetching Instruction decoding Argument fetching Instruction execution Saving result Process interrupt Instruction cycle DMA control points Interrupt control point

30 DMA configurations Single bus for all modules, software control of input/output Single bus, integrated DMA Input/output bus – separated for the peripherials, DMA module is a bridge

31 Single bus, detached DMA controller CPU suspension performed twice during the peripherial device communication bus also used twice

32 Single bus, integrated DMA controller DMA controller supports more than one device transfer requires one bus access, similarly with the CPU suspension

33 Input/ouput bus One bus access (DMA to memory) CPU suspended once

34 External interfaces types Parallel interface – multiple lines, fast devices (hard drives) Serial interface – single line, slow devices (printers) Two-point connection Multi-point connection I/O module must have a buffer for storing data to/from peripherial device

35 FireWire serial bus IEEE-1394 standard Single data line does not require shielding Devices form daisy chain or tree, to one port 63 devices can be plugged in hot plugging of the devices

36 FireWire configuration No terminators!!

37 FireWire protocols layers Physical layers –defines arbitration, data synchronization, coding-decoding, link state, interfaces, signal levels Link layer –Data transmission (sending and receiving packets, cyucle control) Transactional layer –Read, write, blocking

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