LM32 DEVELOPMENTS ONGOING WORK ON TDCs AND OTHER ISSUES (LM32) Diego Real David Calvo CLB group online meeting, 27 March

LM32 DEVELOPMENTS: Next step Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash 2

UDP / IP STACK 3 UDP / IP Xilinx Mac Block FPGA UDP_Tx UDP_ Rx Ethernet Phy

UDP / IP STACK 4 UDP_TX UDP/IP Core UDP_RX IP_Core IPV4 IPV4_TX IPV4_RX MAC_TX_bus MAC_RX_bus UDP_ TX_bus UDP_ RX_bus ARP_TX ARP_RX

l FRAMES FORMAT 5 Source Port (2bytes) Destin. Port (2bytes) Length (2bytes) Checksum(2bytes) Optional Data UDP Datagram UDP Header MAC Header(14bytes) IP Header (20bytes) UDP Header (8bytes) Data (8972 bytes) JUMBO Frame 9000 bytes

l DATA FORMAT: Time Slice 6

LM32 DEVELOPMENTS: Working on it Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash 7

Two days workshop in Genova at the end of April: Secondary LM32 + instrumentation cores TDCs + Acoustic read out 8

the Computing in High Energy and Nuclear Physics Conference CHEP2013 ABSTRACT KM3NeT is a deep ‐ sea infrastructure in the Mediterranean Sea hosting the next generation neutrino telescope. The full telescope volume will be around the 5 km 3 and will detect neutrinos trough the Cerenkov optical effect. The front-end electronics necessary for the readout of the optical module of the telescope is based on a System On a Chip FPGA that provides the digitalization of 31 PMT signals, the time-stamp of the signals with a precision of 1 ns and the synchronization with the rest of nodes with a resolution of also 1 ns. The design and implementation of the front-end electronics system are described. KEYWORDS Neutrino telescope Electronic front-end system 9

2 KC705 have arrives already to the IFIC 1 approved for Genoa 1 approved for Bologna 1 approved for NIKHEF 1 approved University of Athens No news from APC ALTERA has approved also 2 ARRIA V 7S has not yet prepared the Eurostar application and it is probably that they will not apply to it 10

A SVN repository created for KM3NeT svn+ssh://isvn.ific.uv.es/repos/KM3NeT Access via https or ssh: Two possibilities to access : To use a cern account. Send to Diego Real to allow permission to the repository. (already To those that do not have a cern account the IFIC is preparing a restricted IFIC account to allow access to the repository. Under test at the moment 11