1. July,31 2013 IFIC (CSIC – Universidad de Valencia) CLB: MULTIBOOT 1

2. l SPI FLASH : MEMORY MAP Golden Image (bit file) Multiboot Image (bit file) Free Space Base Address Upper Address Stable Image to start up and recovery the system New Image to reconfigure the system Space available in SPI flash memory 2

3. l MULTIBOOT: First test Golden Image (bit file) Multiboot Image 1 (bit file) Free Space 0x00000000 0x00400000 0x00800000 Multiboot Image 2 (bit file) Corrupted.bit Image CRC Failure Golden.bit Image Multiboot.bit Image 3

4. l RECONFIGURATION: VHDL implementation VHDL 4

5. MULTIBOOT: LM32 Wishbone slave Rx_mac2buf I2C Fifo 31 TDCs TDC0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x8) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S M M State Machine SPI S M Flash Multiboot Management & Control M S S 5

6. l MULTIBOOT: Status VHDL reconfiguration Integrate as Wishbone slave Create libraries and driver Slow control using embedded software Write the multiboot images in flash memory using LM32 6

7. l CLB: WORKSHOP 7 11 th -12 th of September Onshore Station CLB and power board schematics and layout Planning Two recommended hotels: http://www.ayrehoteles.com/en/hotel-astoria-palace/ http://www.expohotelvalencia.com/en/index.jsp IFIC - Instituto de Física Corpuscular Edificio Institutos de Investigación c/ Catedrático José Beltrán, 2 (junto TVV, parada tranvía Santa Gemma) E-46980 Paterna - España Coordenadas GPS: W -0.4250 N 39.5151

8. l CLB: PLANNING 8

9. l 9

10. l 10 NEED TO START DOM PRODUCTION IN JULY 2014 -> 40/50 CLBv2 ready to be integrated by July 1.- Implications on the planning of the KC705 – SPEC communication throught WR. Please comment 2.- Reduce from 2 month to 1 month the production of the 25 CLB prototypes: - Negociate in advance with the manufacturer (time enough) - More money (not an issue) - The detailed test will be reduced one month (minor issues delayed) 3.- Increase the number of prototypes from 25 to 60. - 40/50 of them could be ready by July to start DOM production. 4.- Tender launched in december 2013 -> May/June company selected: 4.1.- The company has to know in advance that there will be minor changes in the layout of the tender documentation. 4.2.- The final layout will be ready by end of May 2014 (if current planning still valid and 1 month is gained by reducing the manufature time of the prototypes) 4.3.- The first bach of 100 CLB to be delivered by end July 2014. Testing of the CLB and delivery to the DOM production sites during August 2014 (There will production on August?)

11. l CLB: OTHER ISSUES 11 1.Multiboot on the way. a)Multiboot cabability on the KC705 almost finish b)Work on the SPI to be started in September (after holidays) i.Not only for image change but for DAQ parameter storage 2.Power board: Demokritos working in close collaboration with Genova. CLBv1 power board used as reference i. Review to be done on the Valencia workshop 3.- CLB layout: a.Schematic review to be done on the Valencia workshop b.Possibility to habe the first 4 “gamble” prototypes ready by December (one month in advance with the planning)? Then can be start the test of: a.TDCs b.Hydrophone c.State Machine d.Secondary LM32 e.Multiboot f.Integration of the previous systems c.Probably 4 prototypes are not enough -> Valencia, Bologna, Genova and Nikhef + test (375T and 165T) -> 8 a better number (6 165T – 2 375T). d.Important to check avalavility of components in advance to avoid surprised. FPGA can be purchased as soon as the number of prototypes is decided

12. l CLB: OTHER ISSUES 12 4.- Important to think on the stimulus for the TDCs of the “gamble” prototypes. Virtex 6 signals can be used to supply the Octopus connectors. At some point the prototypes should be connected in a DOM (good mechanic test) and in dark the PMT should be connected and stimulated (Comparisson with CLBv1 results should also be foreseen) 5.- State machine and TDC ready. Integration of the state machine with IPMUX to be done 6.- Ethernet port: To be added to the “gamble” prototypes for debuging Vladimir already make a connection on the KC705 Ethernet port using microblaze Starting to use a opencore in order to integrate it to the secondary LM32. 7.- A minor issue to not forget: On the reference design (firmware and hardware) add a third I2C bus. a) one I2C bus for PMTs configuration b) another I2C bus for Tilt, Compass and temperature c) and the last one for Nanobeacon and Hydrophone 8.- Instrumentation: We need a decision!!