1. KM3NeT CLBv2

2. Implementation issues porting KC705 design to CLBv2 Proto
20 MHz VCXO
I2C tri-state pins
PPS_P/N and FPGA_CLK_P/N LVDS_25 conflict
FLASH_SPI_CCLK on C8
=> For details: see “backup slides”
Note that there is still one single design
Synthesis generics and UCF file determine the platform

3. CLBv2 Proto (= same as KC705 + SoftPLL)
IP/UDP Packet Buffer
Stream Selector (IPMUX)
31 TDCs
Start Time Slice UTC &
Offset counter since
Fifo
TDC0
Time Slice Start
RxPacket
Buffer
64KB
RxPort 1
31 PMTs
RxPort 2
Rx Stream Select
Fifo
TDC 30
wrf_src
Rx_mac2buf
Rx_mac2buf
Rx_buf2data
wrf_snk
Flags
RxPort_m
Management
& Control
aux_master S 6 1
Management
& Config.
State Machine 5 7
Pause Frame
ADC
Fifo 4
Hydrophone 2 3
TxPacket
Buffer
32KB
TxPort 1
Management
& Control
TxPort 2 S
Tx_pkt2mac
Tx_pkt2mac
Tx_data2buf
Tx Stream Select
Multiboot 1 2
Flags
TxPort_m S
Management
& Control
Nano
Beacon
ext_wb S
WB Crossbar
(1x8) M M M S M M M M M M
Debug LEDs
WB Crossbar
(2x3) S M
2nd CPU
LM32 M
SPI S
UART S S S S
Xilinx
Kintex-7
MEM S
I2C
I2C
GPIO
Data
UTC time & Clock (PPS, 125 MHz)
Control
Point to Point interconnection
SPI
Flash
Debug RS232
Temp
Compass
Tilt
Wishbone bus

4. Both LM32 CPUs to be operational!
CLBv2 Proto Results
Ping is operational:
see
WR-timing:
WR Servo in state “track phase”
Calibration parameters can be stored:
I2C EEPROM and SFP are accessible
There is a clock issue:
No fixed latency between VCXO and serial Tx stream (GTX internal PLL; clk_gtx_i -> tx_out_clk_o phase reset)
This was not an issue on the KC705 (I’ll check again!)
I’m starting to get worried a bit… => it needs further study.
Note:
Both LM32 CPUs to be operational!

5. CLBv2 Proto Power consumption and Resource usage
Ping design taken as a reference.
Adding the rest of the system adds resources and power.
The final dissipation and resource usage is only known after integration.
CLBv2 Proto “Ping” ~3.9 W (including debugging mW and 850 nm mW)
Resources:
Number of Slice Registers: ,992 out of 202, %
Number of RAMB36E1/FIFO36E1s: out of %
Number of RAMB18E1/FIFO18E1s: out of %
Number of BUFG/BUFGCTRLs: out of %
Number of GTXE2_CHANNELs: out of %
Number of IBUFDS_GTE2s: out of %
Number of MMCME2_ADVs: out of %
Tentative estimate: XC7K160T Speed grade 1 (slowest) does the job.
To figure out margin try a fit of the integrated design for a 140 MHz clock

6. Other CLBv2 Proto issues
All listed in google document:
KM3NeT_ELEC_2014_001_Doc- Prototype_design_changes_ELEC_draft
Use proper tooling to assemble GBX connectors
Placement of the Nano beacon connector (J22)
!!!Attention!!! The Power connector (J2) has a pin swap as compared to the CLBv1!
The FMC connector screws have a close encounter with components C128, C131, R88 and R89

7. 16 ns phase jump study (seen on KC705)
Last meeting reported a 16 ns phase jump
This appears to be a non-issue:
Due to the PHY TxOutClk and RxOutClk not being locked when connected to a Linux machine.
In that case the SoftPLL is not locked so the RxOutClk is related to the Linux Machine and TxOutClk is our (free running) VCXO.

8. Calibration
Extensive contact with Greg Daniluk and Javier Serrano.
“Relative” versus “Absolute” calibration
WR calibration document describes “relative” calibration, i.e. with respect to a WR device that is elected to be “THE” calibrator.
Relative calibration is an “easy” procedure but, …
… Calibrated WR devices that are calibrated with different WR-calibrators will not provide exact timing.
With respect to standardization “absolute” calibration would be better!
It is more reliable over time
all WR devices can be exchanged (different vendors, globally).
… but it is more difficult to achieve.

9. Calibration We learn a lot about the calibration issues!
The calibration job is done when using a “KM3NeT” WR-calibrator (i.e. use relative calibration)
This needs to be a single golden KM3NeT WR device to be used over the lifetime of the detector…
We plan to do more study with respect to “absolute” calibration.
More reliable over time and exchangeable with other WR gear globally.

10. WR PTP Core New release (version 2.1) Our input is not yet integrated
Our input is not yet integrated
Currently being processed by Greg Daniluk:
git branch “stuff_from_peter”
=> Keep our files for the moment and wait for Greg to merge our input in the git master.

11. “Critical Design Review”? Are we already able to review the design?
Workshop January
“Critical Design Review”?
Are we already able to review the design?
Suggestion: Lets have a workshop and start to work with the people involved on the integration of the CLBv2 firmware.

12. Status Listing Currently: To do list (in order of priority):
KC705 -> CLBv2 Proto porting
Calibration
To do list (in order of priority):
Study: Reset button puts the system in a weird state
Implement Rx Pause frames
Wish list:
LM32 debugger

13. Backup Slides More details…

14. Implementation issues on CLBv2 Proto
20 MHz VCXO
KC705 design uses an IBUFGDS
CLBv2 uses IBUF
Due to the issue were the single ended 20 MHz VCXO signal was routed to a “negative” defined FPGA input pin.
Issue solved on CLBv2
I2C tri-state pins
KC705 + SoftPLL: pins must be driven ‘Z’
CLBv2 pins no longer exist
Issues solved by entity KC705_Support and generic g_use_clbv2 (default true)

15. Implementation issues on CLBv2 Proto
PPS_P/N and FPGA_CLK_P/N are LVDS
LVDS_25 conflicts with VCCO3.3 on BANK 116
Note that FPGA_CLK_P/N is an input in the current design…
Issues solved by generic g_use_clbv2_proto selecting either:
One OBUFDS (differencial output)
Two complementairy driven OBUF (single ended output) mimicing a differencial signal
This signal needs to be solved on future PCBs for the next series.

16. Implementation issues on CLBv2 Proto
FLASH_SPI_CCLK on C8
C8 is a dedicated configuration pin…
Diego => “use the primitive STARTUPE2”