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February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.

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Presentation on theme: "February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1."— Presentation transcript:

1 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1

2 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology White Rabbit SPEC-NIC (= “one-port switch”) WR-Timing and Ethernet WR-NIC 2 PPS Use SPEC with NIC firmware/software in Grand Master mode: http://www.ohwr.org/projects/wr-nic/wiki http://www.ohwr.org/projects/wr-nic/wiki PPS 10MHz PPS GPS Timing Reference (Grand Master Mode)

3 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Jumbo frames are not received… ◦ This is also an issue for the WR switch V3.3! Not all UDP packets are received: According to Miguel Jiménez López this is a speed issue and we should look forward to a DMA core in wr-nic design WR-NIC issues 3 All 15 received by intel PRO/1000 PF Only first 8 received by SPEC-NIC

4 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology WR-Timing and Ethernet (multi-port) WR Switch 4 PPS 10MHz PPS Use switch as is: ◦ no broadcast (yet) ◦ Standard firmware/software Timing Reference Grand Master Mode

5 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology NIKHEF has a pioneer switch that was not up to date. We were not able to do the Flash procedure with out Ubuntu 12.04 machines (tried two) Switch Core Board was returned to 7_Sols for flashing. No problem found. Flashing okay. Flashing via laptop Ubuntu 13.04 sometimes failed => cause unknown… According to 7-Sols there is a procedure found to successfully flash 100% of the time. Received the SCB back just yesterday… WR Switch 5

6 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Firmware integration 6 Adding TDC, Hydrophone, connection to IPMUX, Multiboot => Still a lot of work to be done! Empty State machine, David is working on it ◦ => TDC and AES are optimized away by the synthesis tool! TDC sources in place (Valencia) AES sources in place (Genova) Empty place holder, (Valencia)

7 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Firmware integration other issues 7 IPMUX UDP Channel connections: 0:TDC 1:AES 2:Packet generator  15 UDP packets (data payload 2,4,6,… 30 bytes) 3:Packet generator  2 Jumbo UDP packets (data payload 8972 bytes) ◦ Note that Channel 2 and 3 connect to a push-button/dip- switch packet generator for test purposes. Added a ref_clk_lock signal ◦ Note that clk_sys is always running (62.5 MHz for LM32 and wishbone) ◦ Ref_clk_62_5, ref_clk_125, ref_clk_250 may be interrupted during WR startup. Pay attention to the ref_clk_lock signal!

8 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Firmware integration 8 Fruitful Vidyo: David, Vladimir, Antonio, Peter ◦ But… still some confusion to solve! StMachine: ◦ Chops data into UDP packet size chunks. Packets get Time-Slice info and index number ◦ StMachine does not know the data type (although it should know the data word size (n*16-bits) AES Frame = all audio for one Time-Slice ◦ First UDP packet of a Time Slice contains the AES- Info word. ◦ This is the most straightforward implementation! ◦ If first packet gets lost you lose Audio for one Time- Slice (although audio samples can still be re-processed offline). Is this acceptable?

9 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Thermal Pictures CLBv2-Proto 9 Running WR PTP in TRACK_PHASE ◦ Ambient ~ 23 degrees ◦ FPGA ~ 36 degrees ◦ “Hot Spot” ~ 37 degrees (Clock driver U4)

10 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Thermal Pictures CLBv2-Proto 10 Running WR PTP in TRACK_PHASE

11 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Thermal Pictures PBv2.1 11 Ambient ~ 23 degrees Fully loaded: ◦ 1V0 => 3A ◦ 1V8 => 1A ◦ 2V5 => 1A ◦ 3V3 => 3A ◦ 3V3 PMT => 1A ◦ 5V => 1A “Hot Spot” switchers ~ 38 degrees

12 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Thermal Pictures PBv2.1 12

13 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Questions? 13

14 February 26, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Backup Slides More details… 14


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