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KM3NeT CLBv2
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Connect WRPC and IPMUX => simulation
Packet Transmit Frame Generator IPMUX Frame Generator
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WRPC Transmit path Auto Negotiate
First try to send a packet thru WRPC serdes_tx continuously transmits the sequence below: IEEE802.3 Table 36-3: /C1/ = <K28.5><D21.5> = BC B5 /C2/ = <K28.5><D2.2> = BC 42 Auto Negotiation is active… Therefor no packets are forwarded Change the wrc_main.c: ep_enable(1, 0); // Auto Negotiate switched off for simulation /C1/ /C2/
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WRPC Transmit path First Packet received in simulation!
SFD preamble MAC_dst MAC_src LenTyp CRC IP_src IP_dst UDP_src UDP_dst UDP_len UDP_chks Payload /T/R/
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WRPC Transmit path Small packets are dumped
port 8192 2x 58 bytes => dumped! Minimum size & Jumbo port 8193 2x 60 bytes port 8194 2x 62 bytes port 8195 2x 9014 bytes
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WRPC Transmit path Jumbo Packets received!
UDP port 8192 fifo0a.bin fifo0b.bin UDP port 8193 fifo1a.bin fifo1b.bin Jumbo UDP port 8194 fifo2a.bin fifo2b.bin UDP port 8195 fifo3a.bin fifo3b.bin
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WRPC Transmit path Small packets are not padded
SFD preamble MAC_dst MAC_src LenTyp CRC IP_src IP_dst UDP_src UDP_dst UDP_len UDP_chks Payload /T/R/ However… This packet is dumped by Linux because it is smaller than the minimum Ethernet packet size! (Payload only one 16 bit word) MAC frame and packet specifications (IEEE802.3 clause 3) paragraph 3.1.1, figure 3-1: add/remove padding is a MAC task of the MAC It was not padded with zero’s in the WR endpoint bug! ….fw\WRPC\modules\wr_endpoint\ep_tx_framer.vhd Contacted Tomasz Wlostowski and Grzegorz Daniluk
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WRPC Transmit path “new” ep_tx_framer with padding
Try all frame sizes 2, 4, .. , 30 bytes Padded Jumbo
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Stream Selector (IPMUX)
Packet Transmit This includes verification (thru simulation) of proper pipeline stall assertion and de-assertion at any point during data transfer. IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Fifo TDC 30 Rx_mac2buf Rx_mac2buf Rx_buf2data Rx Stream Select Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Done! Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S S Xilinx Kintex-7 MEM S UART S I2C I2C S GPIO S Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus
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Stream Selector (IPMUX)
Packet Receive Done! IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Fifo TDC 30 Rx_mac2buf Rx_mac2buf Rx_buf2data Rx Stream Select Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine This includes verification (thru simulation) of proper pipeline stall assertion and de-assertion at any point during data transfer. 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S S Xilinx Kintex-7 MEM S UART S I2C I2C S GPIO S Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus
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Currently: integrate & connect LM32_2nd (FIFO interface)
IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control aux_master S 6 1 State Machine 5 7 Pause Frame Management & Config. ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S UART S S S S Xilinx Kintex-7 MEM S I2C I2C GPIO Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus
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Stream Selector (IPMUX)
Next: Connect IPMUX management (Currently default IP and MAC addresses are used) IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Fifo TDC 30 Rx_mac2buf Rx_mac2buf Rx_buf2data Rx Stream Select Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S UART S S S S Xilinx Kintex-7 MEM S I2C I2C GPIO Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus
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Stream Selector (IPMUX)
LM32_2nd integration IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 wrf_src Rx_mac2buf Rx_mac2buf Rx_buf2data wrf_snk Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S UART S S S S Xilinx Kintex-7 MEM S I2C I2C GPIO Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus
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LM32_2nd integration issues (1)
LM32_CORE uses profile “medium_icache_debug” “debug” instantiates Kintex7 BSCANE2 primitive. There are four BSCANE2 implementing USER1 through USER4 JTAG instructions available. Currently one USER1 is used (somewhere deep in the LM32 code): Lm32_top -> jtag_cores -> jtag_tap platform\kintex7\jtag_tap.v So both LM32s try to implement the same instruction Work-around: One of the LM32_COREs is set to “medium_icache” Better: try to set USER instruction attribute via synthesis tool…
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LM32_2nd integration issues (2)
BMM now contains both: LM32_wrpc memory space LM32_2nd memory space Use “tag” in the data2mem command to point out which “elf” file should go where.
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LM32_2nd integration issues (3)
How do we connect both LM32’s with respect to their memory maps? SDB SDB SDB SDB IO IO MEM MEM ? MEM S LM32 2nd M WB Crossbar (2x3) LM32 WRPC (3x2) SDB SDB 0x 0x SDB SDB 0x 0x IO IO 0x 0x ? MEM MEM 0x 0x
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LM32_2nd integration issues (4)
Small changes on the entity definition: g_profile => "medium_icache_debug“ Wishbone connection to WRPC Wishbone connection to ipmux LM32_2nd users will be confronted with this when they update their LM32_2nd SVN working copies in the near future.
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Soon available for TDC testing and further integration
IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 wrf_src Rx_mac2buf Rx_mac2buf Rx_buf2data wrf_snk Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S UART S S S S Xilinx Kintex-7 MEM S I2C I2C GPIO Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus
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Resources used so far (KC705 => Kintex7-325):
Number of Slice Registers: 8,928 out of 407, % Number of Slice LUTs: ,181 out of 203, % Number of LOCed IOBs: out of % Number of RAMB36E1: out of % Number of RAMB18E1: out of % Number of BUFG/BUFGCTRLs: 5 out of % Number of GTXE2_CHANNELs: 1 out of % Number of MMCME2_ADVs: out of %
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Stream Selector (IPMUX)
Current Visual Status IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 wrf_src Rx_mac2buf Rx_mac2buf Rx_buf2data wrf_snk Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S UART S S S S Xilinx Kintex-7 MEM S I2C I2C GPIO Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus
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Status Listing Done: Currently: To do (in order of priority):
LM32 + WB-Crossbar + DPRAM + UART Soft-PLL FMC layout WR without PCI-express Deterministic PHY 1-wire Endpoint (= MAC) Fabric redirector Currently: Intergrating / Connecting LM32_2nd Soft PLL (hardware + software). Still under study… Calibration procedure PPS generator To do (in order of priority): Mini-nic <= Complex, but seems to work (no further action at the moment) SysCon <= easy (no further action at the moment) LM32 debugger
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Finally arrived October 16 (@ NIKHEF)
GBX connectors Delivery was scheduled for September 16 Delayed until October 10… 162 connectors Finally arrived October 16 NIKHEF)
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