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CLB: Current status and development
IFIC (CSIC – Universidad de Valencia) 13 Nov, 2013
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TDC: MODIFICATIONS & OPEN QUESTIONS
l TDC: MODIFICATIONS & OPEN QUESTIONS Pulse width larger than 255 ns will not be discarded?: 1.- Should we change the data format?More bits for width? 2.- Should we split it in differents hits?? FIFO T_STAMP (ns) WIDTH (ns) 30 10 60 254 16 626 15 10 516 15 30 20 50 Pulse width = “ ” reserved for new time slice
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TDC: MODIFICATIONS & OPEN QUESTIONS
l TDC: MODIFICATIONS & OPEN QUESTIONS Pulse width larger than 255 ns will not be discarded What about if change of time slice is during the width?? 1. Should we stored in the previous time slice?? FIFO CH 1 T_STAMP WIDTH 30 10 60 254 16 Special_mark 255 366 15 New time slice 10 516 15 30 20 50 200 316 2. Should we split it in differents time slices ?? 3. Other options…
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FIFOs FOR JAVA TEST STATE MACHINE: TEST l TDC memory integrated
31 TDCs Fifo TDC0 TDC MEMORY State Machine 31 PMTs Fifo TDC 30 TDC memory integrated Hydro memory soon Management & Control S ADC Fifo Hydrophone HYDRO MEMORY State Machine Management & Control S WB Crossbar (1x8) M M M M M M M M M M UART S JAVA APLICATION (GENOVA) Debug RS232
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STATE MACHINE: CURRENT DESIGN
l STATE MACHINE: CURRENT DESIGN TDC FIFO Time Stamp (32 bits) Pulse Width (8 bits) Time stamp 1 Width 1 Time stamp 2 Width 2 Time stamp 3 Width 3 ………………………. ……………. “ ” + Absolute time (28 bits) “ ” Absolute time (40 bits) TIME SLICE 1 NEW TIME SLICE TIME SLICE 2
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INTEGRATION NOT YET (But soon) DONE
l INTEGRATION NOT YET (But soon) DONE 2nd LM32 TDC and state machine MULTIBOOT UART 2x I2C SPI White Rabbit Hydro 4x I2C
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Comunication Interfaces
FIRMWARE OVERVIEW State Machine White Rabbit IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 TDC Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S State Machine Pause Frame Management & Config. ADC Hydro Fifo Hydrophone TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot Flags TxPort_m S Management & Control Nano Beacon Multiboot S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs MEM S WB Crossbar (3x2) S M 2nd CPU LM32 M SPI S UART S S S Xilinx Kintex-7 I2C I2C GPIO S Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus Comunication Interfaces 7
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THANKS FOR YOUR ATTENTION!
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