Calorimeter CROC PRR CERN Calorimeter ReadOut Card PRR Tests of the CROC Calo CROC PRR – Tuesday 19 December 06

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC2 Outline CROC v1, v2 and … finally v3 Radiation tolerance Backplane connections Power Supply Fault ECS Clock, L0, ChannelB Data Transfert Debugging capabilities User signals : clock, channelB, L0 Spy Mode Fibre Acquisitions BER tests Data acquisitions (Pattern Generator mode)

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC3 CROC History First version 2004 Two copies of CROC v1 : needed rapidly more than two But the firm that made them disappeared We had to pay for new masks Take this opportunity to correct some wrappings (delay chip polarisation error) Add NIM inputs/outputs This became CROC v2 : 2004 / 2005 CROC v1/v2 have been heavily used since TTC signal production and Data acquisition (through ECS, no fibres) Development of the Front-end boards of the ECAL/HCAL PRS/SPD Test of the Front-end boards produced Already 260 ECAL/HCAL FEB tested CROC at Annecy (v1), CERN (v1+2v2), Clermont (2xv2), LAL (2xv2)

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC4 CROC v3 with respect to v1/v2 Two big modifications : Implementation of the 2 optical mezzanines Change FPGA :ALTERA to ACTEL Pro Asic Radiation tolerance Apart from that, few things have changed : Same header detection Same spy functionalities Same Debugging Signal production L0, Clock divided, ~Channel B But Delatcher for deserializer SPECS Bus Internal 40MHz quartz removed New, simple and clean clock tree

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC5 Radiation Tolerance (I) All the components used on the CROC have been tested for the FEB Latest irradiations : 2005 and 2006 Centre de Protonthérapie d’Orsay Protons 200MeV ~1.2x10 8 particles cm -2.s -1 In Beam 2 APA ProAsic APA300, APA150 3 NIM components 10H124 10H125 : NIM input : NIM output Problems looked at Dose (NIM) SEL SEU protection (APA)

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC6 Radiation Tolerance (II) ACTEL APA No SEL observed ACTEL reports a high resistance >100MeV.cm2/mg to be comp. with 15 An APA cannot be re-loaded safely after 20 krad Some Specs Mezzanine were broken after 35 krad This is not a problem for the CROC : expect 2krad in 10 years (nominal luminosity) No SEU observed on the Sequencer (FEB) More than 240 LHCb year equiv. Luminosity Roughly more than 2 years without SEU for the 26 CROCs Delay Chip SEU Suppose 1 reload/day Limit is more than 1000 years for the CROC Deserializer Proba(SEL) had been measured at GANIL < 2.6x for a 1GeV neutron Less than a SEL in 960 years (1 chip) Less than a problem in 2.3 years (26 CROCs)

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC7 Backplane connections (I) Power Supply Plugged the CROC in a Backplane powered up 2 possible configurations for the +5V Test crate The CROC has always been used in these conditions Standard crate This has to be done (mid-january, today ?) Fault The possibility to switch individually any board of the crate has been tested The pins have been probed for the validation boards The capture of a transition has been observed by manually playing with FEB backplane pins

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC8 Backplane connections (II) ECS Test of writing/reading Pattern RAMs for the 16 FEBs Clock Clock was checked at the level of the boards Good operations of the FEBs : Reading through ECS requires a good clock at the level of the FEB Glue L0 L0 have been sent the corresponding data have been read in the CROC Fe-PGA RAM ChannelB 8 bit checked Front-End Reset – Calibration – B-ID and E-ID reset have been used Data transfert : FEB pattern RAM have been loaded with specific values Calibration and L0 pulses have been sent The values have been read in the CROC Fe-PGA RAM for 15 boards out of the 16 Problem with slot 2 identified : no deserializer output clock (most probably broken) Connectors -> deserializer : pins have been probed. Links are ok Need to do the test with the second CROC If OK -> deserializer will be changed by ALTREL

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC9 Debugging Capabilities Fe-PGAs The storage of the data in the Fe-PGA is tested All the FEB have been checked (except slot 2!) Spy-PGA Signal generation : L0, clock divided, Channel B What is missing : some firmware (essentially Spy-PGA) Address Table and FIFO implementation in Spy-PGA Handshake between Fe-PGA and Spy-PGA No new / removed line on the PCB with respect to v2 We plan to test it BEFORE the production production should be launched in mid-january

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC10 Test Bench CROC TELL1 (FEB) PC-CROC Network Connection CCPC-LAL Server TTCvx/vi

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC11 TTC System TTC produced by a TTCvi (borrowed from Clermont : Thanks !) TTCvx Clock : CROC v3 has no quartz TTCrq clock always in use Possibility to control the VME Crate Same PC as CROC configuration Sends Channel B L0 VME Access Random (1Hz, 1kHz, 5kHz, …, 100kHz) Sends a trigger on network request Acknowledge provided for handshake TTCviTTCvx PC-CROC control NIM output TTCrq output

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC12 Data Acquisition : BER test 16 GOLs configured in Test Mode (I2C bus) TELL1 loaded with ST software DAQ BER launched ConditionsBER (transf. bits) 8 fibres(Left), no attenuation148x fibres, no attenuation66x fibres, no attenuation130x fibres (Left) with 6db15x fibres (Left) with 9db20x fibres, 6db(Left), 9db (Right)350x10 12 TELL1 console No error seen 16 fibres out of 24

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC13 A data acquisition system Client/Server was developped to check the data transfer The CROC Fe-PGA RAMs are loaded with predefined values The CROC is configured in Pattern generator mode The PC-CROC triggers a TTCvi/vx trigger Captured by the CROC which produces A L0 (L0 TTCrq : default usage of the CROC) Several L0s as defined by the requested configuration use Debug Trigger generator capabilities of the CROC (TTCvi -> NIM input) The PC-CROC sends a message on the LAL networks giving the number of L0 triggered The message is received by the Credit-card PC of the TELL1 The CCPC reads the TELL1 FIFO and checks the data values wrt what is expected The CCPC sends back on the LAL network a message saying that a new sequence may start Data Acquisition : CROC Data (I)

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC14 Data Acquisition : CROC Data (II) What is checked : 16 FEB (=Fibres) x 34 words x 32 bits per L0 Two modes : L0 is due to the TTCrq Full check of the system from the TTCrq to the TELL1 But slow rate : 1 million L0s in ~ 17 hours TTCvi signal is used to make a L0 sequence Produced sequences of 7 consecutive L0s (34 words x 7 L0 = 238 ~ 256 (TELL1 FIFO depth)) Rate : 1 million sequence in 40 hours (but a sequence is 7 consecutive L0s) Test fibre synchronisation method ConditionsTriggerConsec. L0s 16 fibres, No attenuation 10 6 (TTCrq) L01 16 fibres, 9db(Left), 6db (Right) 10 5 (TTCrq) L fibres, 6db(Left), 9db (Right) 3x10 5 (TTCrq) L01 16 fibres, 6db(Left), 9db (Right) 5x10 5 (External)7

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC15 Production Test at LAL Test Bench will have crate with 16 FEBs a TELL1 board Delatch every board sequentially : visual check ECS Write and read back RAM in the 16 FEBs → SPECS Bus Write/read Optical Mezzanine and TTCrq registers → I 2 C Buses Write/read PGA registers and RAM → parallel Buses Backplane data transfert / TTCrq connectivity Load 16 FEBs with RAM patterns Send ChannelB and L0 with TTCvi/TTCvx Read back information in the CROC Fe-PGA RAM Data transfert through backplane L0 and ChannelB propagation Header detection Spy Functionality Re-use the FEB production test Plan to perform a full acquisition of the crate Optical Connections BER tests Acquisition test with FEBs and Pattern generator Mode in single/multi L0 modes 1 CROC tested per half day (?) -> 3 weeks for the full batch (?)

Frédéric MACHEFERT Tuesday 19 December 2006 PRR CROC16 Conclusions A DAQ test is planned in January with CROC v3 At our disposal (Build 156) CROC v3 A CRACK TELL1 Trigger L0 with ODIN board Read back data with the TELL1 board SPY DAQ implementation on going in the Spy-PGA Has to be tested before production launched same PCB implementation as CROC v1/v2 No problem seen : small corrections on the PCB APA 150/300/450 : A problem has been identified with the ACTEL PRO Asic Sometimes component does not work : JTAG scan clears the problem Affects ECAL/HCAL (Seq., Glue), PRS/SPD (Trig.) FEBs and CROC Still under investigation