1. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 1 OTIS (Outer Tracker Time Information System) A TDC for LHCb 8 th Workshop on Electronics for LHC Experiments September 9 – 13, 2002 Colmar, France OTIS Group, University Heidelberg: Harald Deppe Uwe Stange Ulrich Trunk Ulrich Uwer

2. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 2 Contents Overview Outer Tracker, Front End Electronics & OTIS OTIS Chip Concept Components of the OTIS Chip OTIS1.0 Prototype Measurements Summary

3. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 3 LHC/LHCb/Outer Tracker LHCb-Detektor: LHC: Physics with heavy quarks LHCb: Search for CP violation Detektor: magnetic spectrometer in forward direction The Physics Institute of the University of Heidelberg participates since middle of 2000 in the development of outer tracker modules and frontend electronics

4. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 4 Outer Tracker / FE Drift time measurement Mounting on detector Approx. 50,000 channels Data of 4 TDC (32 chan- nels each) gets serialised and transmitted optically (1.28GBit/s) Chip Requirements: 1ns resolution (6 bit) drift times of up to 50ns 40MHz, clock driven design 1.1MHz L0 trigger rate up to 10% occupancy 4µs trigger latency radiation hard design (pipeline length: 160) 9.6GBit/s 4 x 320MBit/s

5. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 5 OTIS: Concept Components: 32 maskable channels DLL, HitRegister, PrePipeline: 6 bit drift time generation, playback data feed in Pipeline, Derandomizing Buffer: Intermediate data storage, compensation of trigger rate fluctuations Control Algorithm: Memory and trigger management, data output Slow Control Interface: Programming the chips behaviour DAC: ASD-Chip bias

6. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 6 OTIS: DLL, HitReg, Decoder Clock Delay Chain Phase detector Charge pump Hit Signal DQ 64 Time bins ( 390ps nom. resolution) 64 Hit registers QDQD Decoder 64:6 6 bit drift time V ctrl

7. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 7 OTIS: DLL, HitReg, Decoder Clock Delay Chain Phase detector Charge pump Hit Signal DQ 64 Time bins ( 390ps nom. resolution) 64 Hit registers storing a picture of the Hit Signal: QDQD Decoder 64:6 6 bit drift time V ctrl Time 0..01110.. 0

8. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 8 OTIS: DLL Prototype Dynamic Range V ctrl /mV Results Dynamic range: V ctrl : 1V Lock range: f lock : 29-56MHz @ 300K T lock : 10-90°C @ 40MHz Lock time: t lock < 1µs Differential nonlinearity: DNL = 0,51 ± 0,03 LSB ( 190ps)

9. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 9 OTIS: Pipeline, DBuffer Realised as dual ported SRAM (164 + 48) x 240Bit x 40MHz 1.1GByte/s low power design Test chip OTISMem1.0 fully functional expected behaviour confirmed (operational up to 100MHz)

10. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 10 OTIS: Control Algorithm Management of memory, trigger and data output. Verification of critical parts on FPGA. Data format: First hit out of 1, 2 or 3 BX Single Hit TDC 8bit drift times Independant from occupancy Fixed read out length Data format guarantees synchronous operation of all TDC Hit PositionData 1. BX 00XXXXXX 2. BX 01XXXXXX 3. BX 10XXXXXX No Hit 11000000 Bit0.. 3132.. 39...280.. 287 DataHeaderDrift Time 0...Drift Time 31

11. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 11 OTIS: Data format (planned) Bit0..3132..127128..133... 122+(6n)...127+(6n) DataHeader3 * Hit-InfoDrift Time 1...Drift Time n Bit0..3132..9596..101... 90+(6n)...95+(6n) DataHeader2 * Hit-InfoDrift Time 1...Drift Time n Bit0..3132..6364..69... 58+(6n)..63+(6n) DataHeader1 * Hit-InfoDrift Time 1...Drift Time n Data format for 1, 2 or 3 BX per trigger (programmable, truncatable to 900ns) 1 BX per trigger (100% mean strip occupancy w/o truncation) 2 BX per trigger (50% mean strip occupancy w/o truncation) 3 BX per trigger (27% mean strip occupancy w/o truncation)

12. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 12 Contents Overview Outer Tracker, Front End Electronics & OTIS OTIS Chip Concept Components of the OTIS Chip OTIS1.0 Prototype Measurements Summary

13. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 13 OTIS1.0 Prototype First prototype with basic functionality ~700.000 transistors 5100µm x 6000µm Tape out: 15/04/2002 Delivery: 29/07/2002 Small test PCB with possibility to connect ASD and GOL chips

14. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 14 OTIS Under Test (1) DLL Lock Time Ch1: Clock Ch2: notReset Ch3: V ctrl Power Consumption 185mA or 465mW after PowerUp reset 220mA or 550mW operation @ 40MHz V ctrl 1.1V T lock 1µs

15. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 15 OTIS Under Test (2) Read Out Sequence Debug Signals Sequence Start Sequence Stop Data (8bit) Correct memory and trigger management Correct frame length Correct timing and behaviour of Correct data encoding for debug signals- header - drift times HeaderDrift time pattern

16. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 16 OTIS Under Test (3) Drift Time Measurement: Unexpected behaviour of the encoded drift time: under study Workaround to procede with test: double hit pre- charges the decoder preliminary

17. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 17 Preliminary Status OTIS1.0 PowerUp Resetas expected Power Consumption550mW DLL: Lock Time 1µs Lock Lostnot observed DACas expected Slow Controlas expected Fast Control: Memory and Trigger Management, Data Output, Debug Features no errors found Memory Selftestproblems Drift Time Encodingnot yet understood

18. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 18 Outlook Further investigations concerning drift time encoding Study more chips, performance tests, random trigger tests,... Operation with detector prototype Commissioning of the read out chain including TTCrx

19. Harald Deppe, Uwe Stange, Ulrich Trunk, Ulrich Uwer Physikalisches Institut Universität Heidelberg 19 Summary OTIS TDC Chip: 32 channel TDC, 6 Bit drift time resolution 40MHz, clock driven architecture 160 events deep pipeline 1.1MHz trigger rate radiation hard Prototype OTIS1.0 at hand since 6 weeks: almost fully functional