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1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 3 Sequential Logic Design.

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1 1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 3 Sequential Logic Design

2 2 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.1 Cross-coupled inverter pair

3 3 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.2 Bistable operation of cross-coupled inverters

4 4 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.3 SR latch schematic

5 5 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.4 Bistable states of SR latch

6 6 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.5 SR latch truth table

7 7 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.6 SR latch symbol

8 8 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.7 D latch: (a) schematic, (b) truth table, (c) symbol

9 9 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.8 D flip-flop: (a) schematic, (b) symbol, (c) condensed symbol

10 10 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.9 A 4-bit register: (a) schematic and (b) symbol

11 11 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.10 Enabled flip-flop: (a, b) schematics, (c) symbol

12 12 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.11 Synchronously resettable flip-flop: (a) schematic, (b, c) symbols

13 13 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.12 D latch schematic

14 14 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.13 D flip-flop schematic

15 15 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.14 Example waveforms

16 16 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.15 Solution waveforms

17 17 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.16 Three-inverter loop

18 18 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.17 Ring oscillator waveforms

19 19 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.18 An improved (?) D latch

20 20 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.19 Latch waveforms illustrating race condition

21 21 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.20 Flip-flop current state and next state

22 22 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.21 Example circuits

23 23 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.22 Finite state machines: (a) Moore machine, (b) Mealy machine

24 24 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.23 Campus map

25 25 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.24 Black box view of finite state machine

26 26 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.25 State transition diagram

27 27 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.26 State machine circuit for traffic light controller

28 28 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.27 Timing diagram for traffic light controller

29 29 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.28 Divide-by-3 counter (a) waveform and (b) state transition diagram

30 30 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.29 Divide-by-3 circuits for (a) binary and (b) one-hot encodings

31 31 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.30 FSM state transition diagrams: (a) Moore machine, (b) Mealy machine

32 32 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.31 FSM schematics for (a) Moore and (b) Mealy machines

33 33 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.32 Timing diagrams for Moore and Mealy machines

34 34 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.33 (a) single and (b) factored designs for modified traffic light controller FSM

35 35 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.34 State transition diagrams: (a) unfactored, (b) factored

36 36 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.35 Circuit of found FSM for Example 3.9

37 37 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.36 State transition diagram of found FSM from Example 3.9

38 38 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.37 Timing specification for synchronous sequential circuit

39 39 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.38 Path between registers and timing diagram

40 40 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.39 Maximum delay for setup time constraint

41 41 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.40 Minimum delay for hold time constraint

42 42 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.41 Back-to-back flip-flops

43 43 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.42 Sample circuit for timing analysis

44 44 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.43 Timing diagram: (a) general case, (b) critical path, (c) short path

45 45 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.44 Corrected circuit to fix hold time problem

46 46 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.45 Timing diagram with buffers to fix hold time problem

47 47 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.46 Clock skew caused by wire delay

48 48 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.47 Timing diagram with clock skew

49 49 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.48 Setup time constraint with clock skew

50 50 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.49 Hold time constraint with clock skew

51 51 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.50 Input changing before, after, or during aperture

52 52 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.51 Stable and metastable states

53 53 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.52 Synchronizer symbol

54 54 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.53 Simple synchronizer

55 55 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.54 Input timing

56 56 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.55 Circuit model of bistable device

57 57 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.56 Resolution trajectories

58 58 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.57 Spatial and temporal parallelism in the cookie kitchen

59 59 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.58 Circuit with no pipelining

60 60 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.59 Circuit with two-stage pipeline

61 61 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.60 Circuit with three-stage pipeline

62 62 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.61 Input waveforms of SR latch for Exercise 3.1

63 63 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.62 Input waveforms of SR latch for Exercise 3.2

64 64 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.63 Input waveforms of D latch or flip-flop for Exercises 3.3 and 3.5

65 65 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.64 Input waveforms of D latch or flip-flop for Exercises 3.4 and 3.6

66 66 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.65 Mystery circuit

67 67 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.66 Mystery circuit

68 68 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.67 Muller C-element

69 69 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.68 Circuits

70 70 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.69 State transition diagram

71 71 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.70 State transition diagram

72 72 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.71 FSM input waveforms

73 73 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.72 FSM schematic

74 74 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.73 FSM schematic

75 75 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.74 Registered four-input XOR circuit

76 76 Copyright © 2013 Elsevier Inc. All rights reserved. Figure bit adder schematic

77 77 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.76 New and improved synchronizer

78 78 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 3.77 Signal waveforms

79 79 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 01

80 80 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 02

81 81 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 03

82 82 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 04

83 83 Copyright © 2013 Elsevier Inc. All rights reserved. Figure M 05

84 84 Copyright © 2013 Elsevier Inc. All rights reserved. UNN Figure 1


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