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10 December 2012 Clive Max Maxfield All Programmable FPGAs, SoCs, and 3D ICs Part V. Advanced Concepts and Future Trends 1
Programmable Analog 2
High-Speed Serial Interconnect 4
Clock Recovery 5
8-bit/10-bit (8b/10b) Encoding 6
Pre-Emphasis and Equalization 7
Additional Considerations Multiple Standards Fibre Channel InfiniBand PCI Express (PCIe) RapidIO SkyRail 10 Gigabit Ethernet JESD204B etc. Increasing Speeds 3.xxx Gbps 6.xxx Gbps 10.xxx Gbps 28.xxx Gbps (28nm) 40.xxx Gbps (20nm) 56.xxx Gbps (14nm) Optical (10nm) 8
Before 3D ICs 9
Before 3D ICs (cont.) 10
Before 3D ICs (cont.) 11
Early 3D ICs 12
Early 3D ICs (cont.) 13
Dice on SIP Substrate 14
Dice on Silicon Interposer 15
Die on Die 16
A Brave New World 17
State-of-the-Art Today Homogeneous 18
State-of-the-Art Today (cont.) Heterogeneous 19
Rad-Hard, Rad-Tolerant What exactly is radiation? Ionizing versus non-ionizing Particles (α, β, Protons, Neutrons, Heavy Ions) Rays (X-Rays, Gamma Rays, Cosmic Rays…) 20
Rad-Hard, Rad-Tolerant Where can effects occur On-chip registers and SRAM memory cells On-chip combinatorial logic On-chip clock buffers On-chip configuration cells Off-chip general-purpose memory Off-chip configuration memory 21
Rad-Hard, Rad-Tolerant Common radiation-induced problems SEE/SEP (Single Event Effects/Phenomenon) SEL (Single Event Latchup) SEU (Single Event Upset) SET (Single Event Transient) SEFI (Single Event Functional Interrupt) Speed degradation 22
Rad-Hard, Rad-Tolerant Mitigation Strategies Silicon-level (trenches, epitaxial layer) LPT (latchup protection technology) circuit Using special configuration cells TMR (triple modular redundancy) Delaying combinatorial signals Designing fail-safe state machines Lock-step dual processor architectures Design to accommodate speed degradation 23
More Information / Further Reading 24
10 December 2012 Clive Max Maxfield All Programmable FPGAs, SoCs, and 3D ICs Part I. Introduction: The Basics and Benefits of APDs 1.
Baloch 1MAPLD 2005/1024-L Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures SAJID BALOCH Prof. Dr. T. Arslan 1,2.
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Addition Facts = = =
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